Abstract: A network interface system is presented for interfacing a host system with a network, including a bus interface system, a media access control system, a memory system, a security system, and a descriptor management system, wherein the descriptor management system obtains initialization vector information from the host system and provides the initialization vector information to the security system. A method of encrypting outgoing data in a network interface system is provided, comprising providing initialization vector information from a descriptor to a security system in a network interface system, selectively encrypting or authenticating outgoing data using the security system, and selectively employing an initialization vector from the outgoing data to perform CBC encryption of the outgoing data according to the initialization vector information.

Abstract: One embodiment relates to a dual mode radar transceiver. The dual mode transceiver includes a plurality of transmit channels. Each of the plurality of transmit channels is adapted to switch between a first mode and a second mode. The first mode includes a first combination of the plurality of transmit channels adapted to concurrently transmit outgoing signals. The second mode includes a plurality of different combinations of the plurality of transmit channels. Each of the plurality of different combinations has fewer transmit channels than the first combination. Other methods and systems are also disclosed.

Abstract: The inverter housing (1) has a cooling unit (2) for cooling the electronic and/or electric components (4, 5, 5a) of the inverter. The housing (1) of the inverter comprises at least two chambers, the two chambers (7, 8) being separated by a wall (6) for receiving the electronic and/or electric components (4, 5, 5a), the components (5) comprise cooling bodies (4) located on the one side of the wall in the one chamber (7) with the cooling bodies (4) being located on the other side of the wall (6) in the other chamber (5) and the electric or electronic component to be cooled have a high protection grade, the component (5a) being located in the other chamber (8), preferably on the wall side of the wall (6) of the other chamber (8), the other chamber (8) comprising the cooling unit (2).

Abstract: The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The security system is coupled to the memory system and is adapted to selectively perform security processing on incoming and outgoing data. For at least one of receive or transmit processing, the security system comprises one or more encryption pipelines and at least two sets of one or more authentication pipelines. The encryption pipelines are adapted to perform one or more encryption or decryption algorithms. The authentication pipelines are adapted to perform one or more authentication algorithms. The security system is configured to selectively process frames through the encryption pipelines and then through the two sets of authentication pipelines. The system toggles whereby successive frames alternate between the two sets of authentication pipelines.

Abstract: An error detection apparatus for detecting an error in a power signal output by an external device switchable by a switching signal has a comparing unit for comparing the power signal with a reference signal to yield a comparison signal, a switching unit for providing the switching signal dependent on a control signal with the switching unit being designed to disregard the control signal and to ensure that the external device is switched off upon provision of a triggering signal to the switching unit, and a triggering unit for providing the triggering signal depending on the control signal and the comparison signal. Alternatively, the error detection apparatus has an influencing unit for influencing the power signal, such that the power signal fulfils a predetermined relationship to a reference signal in the case of an occurrence of the error, whereas the relationship is not fulfilled in the absence of the error.

Abstract: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.

Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.

Abstract: One embodiment of the invention relates to a dynamically adjustable differential band-pass filter. This band-pass filter includes a first leg that has an input portion and an output portion with a first inductor therebetween. It also includes a second leg in parallel with the first leg, where the second leg has an input portion and an output portion with a second inductor therebetween. The first inductor is symmetrically inter-woven with the second inductor. In some embodiments, the band pass filter is configured to compensate for losses due to the inductors. Other band-pass filters and methods are also disclosed.

Abstract: A circuit arrangement includes a plurality of type-identical and identically operated active components, or separate sections of an active component, and includes a branched wiring structure for the interconnection of component connections. In each case the wiring end portions lie between a branching point and an input of different components or sections, wherein the wiring end portions are formed with predetermined geometrical asymmetry with respect to one another in such a way that there is an electrical symmetry of the interconnection configuration between all the connected type-identical components or sections. More particularly, the impedance values between the branching point and the different inputs and outputs are substantially identical.

Abstract: There is disclosed a cathodic protection system of reinforced concrete structures with discrete anodes obtained starting from a corrugated planar substrate welded to a longitudinal current collector. The anodes of the invention are particularly suitable for being installed rolled in cylinders, with their axis parallel to the current collectors, positioned inside holes made in the concrete of the structure to be protected.

Abstract: A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Abstract: A plasma electron flood system, comprising a housing configured to contain a gas, and comprising an elongated extraction slit, and a cathode and a plurality of anodes residing therein and wherein the elongated extraction slit is in direct communication with an ion implanter, wherein the cathode emits electrons that are drawn to the plurality of anodes through a potential difference therebetween, wherein the electrons are released through the elongated extraction slit as an electron band for use in neutralizing a ribbon ion beam traveling within the ion implanter.

Abstract: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.

Abstract: The subject matter of the invention is a backup power system configured to be a UPS system, with a customer generation system and with a network monitoring device with a switch topology including a first connection node, that is connected to the customer generation system that is connected to at least one automatic disconnection switch including a first switch said first switch being disposed between the customer generation system and a utility grid, and that is connected to a second switch that is connected to one or several loads, said system including a second connection node that is connected to said second switch connected to said load, that is connected to a third switch disposed between the utility grid and the load and that is connected to a fourth switch to which there is connected a standalone inverter with a storage device, and said system including a third connection node, connecting said first switch and said third switch to said utility grid, said customer generation system supplying an AC volta

Abstract: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.

Abstract: The invention specifies a circuit arrangement with a radio-frequency mixer (4) in which a plurality of preamplifiers (1, 2, 3) in a receiver have a common output node (6). This node is connected to a common, broadband radio-frequency mixer (4) via common coupling capacitances (41, 42). Switching means (17, 18; 27, 28; 37, 38) can be used to connect and disconnect the preamplifiers (1 to 3), which can be associated with various frequency bands, independently of one another. The present principle can be applied in multiband receivers in mobile radio and allows integration using little chip area with good radio-frequency characteristics.

Abstract: One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The media access control system comprises one or more local buffers and is adapted to read a second data frame from the memory system while a first data frame is being transmitted to the network. The invention is particularly useful when the memory system has a single memory sharing several clients. When a memory has several clients, there can be instances where a read of the memory by the media access control system is delayed because the memory is busy with a request from another client. The invention helps ensure that such delays do not result in transmission errors and reduces the effect of such delays on overall transmission speed.

Abstract: The invention relates to a phase-locked loop circuit including a phase detector, loop filter and an oscillator. The loop filter is implemented digitally instead of by means of analog components. The chip area required for such a digital loop filter is substantially smaller than an analog equivalence and can be implemented on a single integrated circuit die together with an oscillator, phase detector and possible counters. There is thus no need for the use of external components, greatly simplifying the design and manufacture of the circuit, and having reduced assemblage costs. Further, by means of the digital filter the loop dynamics are also easily changed.

Abstract: The present invention pertains to data security, and more particularly to the security of encrypted data that can be transmitted between computers and the like, as well as stored upon one or more computer systems. A technique is disclosed for efficiently implementing the Rijndael inverse cipher. In this manner, encrypted ciphertext can be efficiently decrypted or converted back into plaintext. Data throughput can be enhanced via pipelining while cost savings can be concurrently achieved as less wafer space and/or die area may be utilized. Adaptations may be made based upon a resulting complexity of implementing a particular design while satisfying a maximum throughput requirement.

Abstract: A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.