Abstract: A circuit for producing one or more regulated auxiliary voltages from a single zero-volt full bridge power stage without degrading the zero-volt switching action. The freewheeling diode used in previous magnetic amplifiers is no longer needed. Transformer current is carried to an auxiliary output inductor through a gate winding of a saturable reactor while a second saturable reactor is reset. Current from the output inductor normally diverted through the freewheeling diode is provided to the transformer through the first saturable reactor just before the transformer provides a pulse of opposite polarity thus discharging the capacitance of the primary switches and enhancing the full bridge zero-volt switching process.

Abstract: When processing an image it is often necessary to combine parts of its matrix mathematically, e.g. to multiply a part of this matrix with a given weighting function. In this context scalar products of vectors are important operations. The invention provides a coding procedure wherein two of the elements of two vectors are transformed to one encoded element, respectively, and are then stored. This has the result that the calculation of the scalar product requires two encoding operations of the elements and one multiplication of the encoded elements. When calculating another scalar product with at least partly the same elements the encoding operations of a number of elements are already done and the stored encoded elements can be used. This has the consequence that the calculation of this other scalar product requires at least partly no encoding operations but only multiplications of the stored encoded elements.

Abstract: A system provides a tool for computing the most typical fuzzy expected value of a membership function in a fuzzy set. The clustering fuzzy expected value system is used in a question answering system. CFEV is computed by the tool is based on grouping of individual responses, that meet certain criteria, to clusters. Each cluster is considered a "super response" and contributes to the result proportionally to its relative size and the difference in opinion from the mean of the entire sample. In so doing, CFEV represents the opinion of the majority of the population, but it also respects the opinion of the minority. A comparison is made with existed tools such as the FEV and the WFEV and the advantages of CFEV are demonstrated by examples for cases where other methods fail to perform.

Abstract: Disclosed is a new torus switch with low latency performance improves torus network connection time by trying multipaths in one single high speed operation. This multipath approach can be directed at establishing a connection between two specific nodes over various alternate routes simultaneously. If only one route is available, the multipath approach will find that path instantaneously and establish the desired connection with minimal latency. If several links are available, the multipath method establishes the desired connection over only one of the available links and leaves the other options free to be used by other connections. In addition, routing at intermediate torus network stages improves over the wormhole approach.

Abstract: A method and apparatus for implementing intelligent priority functions at individual switching apparatus devices which comprise switching networks. The intelligent switching functions are capable of operating in real time systems with high efficiency. The switching apparatus has the capability at each stage of the network to make and/or break connections on a priority basis. If a connection is requested at a switch stage and the connection is being used by a lower priority device, the low priority connection is interrupted (broken) and the requested higher priority connection is established. After the high priority connection has completed its usage of the connection, the high priority connection is broken and the lower priority connection is re-established.

Abstract: A broadcast/switching apparatus makes input port to output port connections on a requested basis quickly and dynamically in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new asynchronous approach to resolve either broadcast or multi-cast contention among input ports. The normal mode of the broadcast/switch apparatus requires absolutely no synchronization among any of the input and output ports which interface to the apparatus. The broadcast/switch apparatus also incorporates a new accept protocol that enables a positive feedback indication to be returned to the sender of a multi-cast or broadcast operation to inform it that the multi-cast or broadcast transmission was correctly received by all elements involved in the multi-cast or broadcast.

Abstract: A DC to DC power converter circuit has a current fed inverter with a series connected first diode and a capacitor connected in parallel with the legs of the inverter. The diode is poled to provide current to the capacitor at the beginning of each inverter switching cycle as energy is passed from the circuit to an output transformer-rectifier circuit. A recirculation inductor and an additional diode are connected in parallel with the legs of the inverter with the additional diode poled to recirculate current in the recirculation inductor. Then a switch between the junction of the capacitor and first diode and also between the additional diode and recirculation inductor provides for discharging of the capacitor without power dissipation during the inverter operation instead of dissipating and losing the energy. Thus the recirculation is accomplished by few components to provide a lossless clamp circuit for recirculating the energy in the circuit from the capacitor back to the recirculation inductor.

Abstract: A communications processor serves a group of several workstations with audio and video transmission processing for the purpose of providing video conferencing. The communication processor utilizes artificial intelligence software to read the connection. Conversion rules are contained in tables so that the system can react to the communications environment. The system is coupled for processing optical signals for low cost communication and video conferencing with audio and video communications within the facility area and for long haul transmission. The communication processor provides audio and video communications under instantaneous constraints of the transmission medium and instantaneous degree of loading or usage. Bandwidth, resolution and transmission rate are adjustable to fit the constraints at the time a request for service is made. A workstation initiates a request for service. A request for service includes data about the nature or type of service and signal destination.

Abstract: Disclosed is multi-media switching apparatus for performing digital, analog, and/or optical communications amongst multiple nodes over switching networks. The key aspect of the present invention is the full parallel aspect of the switching apparatus which supports n simultaneously, low-latency connections, where n is the number of functional elements interconnected by the switching network. Any of the n simultaneous transmissions can be digital, analog, or optical in any proportion. In addition, the present invention can also serve as a high-speed distributed controller for the purpose of of selecting analog or optical switches for information transfer between elements of the system.

Abstract: A system provides question answering based on fuzzy logic. The proposed system provides the capability to assess if a database contains information pertinent to a subject of interest by evaluating each comment in the database via a fuzzy evaluator which attributes a fuzzy membership value indicating its relationship to such subject. An assessment is provided for the database as a whole regarding its pertinence to the subject of interest, and consequently comments that are considered as irrelevant to the subject may be discarded. The system has been developed for the examination of databases and evaluated by testing against those which were created for assessing whether computer system development databases contain information pertinent to the functional changes that would occur in the development cycle. The system can be applied with minimal changes to a variety of circumstances provided that the fundamental assumptions for the development of the membership functions are respected for the application.

Abstract: A SYNC-NET apparatus synchronizes processor nodes of a parallel system over a multi-stage communication network that normally transmits data between nodes as point-to-point communications, broadcast, multi-cast, or multi-sender transfers. The apparatus performs priority driven arbitration over the network to resolve conflicts amongst multiple processing nodes simultaneously requesting use of the multi-stage network for performing barrier synchronization over the network in relation to the same or different barriers. The apparatus uses a special capability multi-stage network that can support only one barrier synchronization operation at any given time, and which makes it necessary to perform a priority arbitration to determine which barrier synchronization gets performed first, second, and so on. Any number of processor nodes can arbitrate simultaneously for use of the barrier synchronization facilities, and the arbitration will be resolved quickly and consistently by selecting the highest priority requestor.

Abstract: Disclosed is a method and apparatus for improving the performance and connection establishing capability of multi-stage switching networks by providing additional intelligent features in the individual switching apparatus devices at each stage of the network. The invention method is particularly effective in asynchronous circuit-switched networks. The most important feature to be added is adaptivity of the switching apparatus; where adaptivity means the ability of each switching element to determine for itself which of several optional alternate paths to try at each stage of the network based on availability. This is a better approach because it brings the decision directly to the switching apparatus involved, which has the data required to make an intelligent path selection decision to circumvent blocking in the multi-stage network.

Abstract: A triple modular redundancy computing system including three asynchronously connected processing elements, each having its own memory, a plurality of arbiters cross connecting processor elements for enforcing synchronization for tasks and for voting arbitration on output and without voting for inputs.

Abstract: A neural network architecture consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neuron processing elements. Neural networks are modelled using a sequential pipelined neurocomputer producing high performance with minimum hardware by sequentially processing each neuron in the completely connected network model. An N neuron network is implemented using multipliers, a pipelined adder tree structure, and activation functions. The activation functions are provided by using one activation function module and sequentially passing the N input product summations sequentially through it. One bus provides N.times.N communications by sequentially providing N neuron values to the multiplier registers. The neuron values are ensured of reaching corresponding multipliers through a tag compare function. The neuron information includes a source tag and a valid signal.

Abstract: A mechanism translates a particular macroinstruction into its associated microprogram routine in a general purpose microprogrammed computer. The macroinstruction is capable of execution by either hardware or by microprogram. A table-look up approach is employed for a microprogrammed macroinstruction. The table is embedded in random-access-memory and contains entries representing the origins of various microprogram routines to execute the macroinstruction. The table entries are addressed by bits generated from the operation-code of the macroinstruction. The output of the table is used to address a single level control store containing the microprogram routines. Hardware is assembled in a single facility that is accessible by the microprogram routines to minimize the size of the microprogram routines required to execute the macroinstruction.

Abstract: A scalable flow virtual learning neurocomputer system and appratus with a scalable hybrid control flow/data flow employing a group partitioning algorithm, and a scalable virtual learning architecture, synapse processor architecture mapping, inner square folding and array separation, with capability of back propagation for virtual learning. The group partitioning algorithm creates a common building block of synapse processors containing their own external memory. The processor groups are used to create a general purpose virtual learning machine which maintains complete connectivity with high performance. The synapse processor group allows a system to be scalable in virtual size and direct execution capabilities. Internal to the processor group, the synapse processors are designed as a hybrid control flow/data flow architecture with external memory access and reduced synchronization problems.

Abstract: The Pyramid Learning Architecture Neurocomputer (PLAN) is a scalable stacked pyramid arrangement of processor arrays. There are six processing levels in PLAN consisting of the pyramid base, Level 6, containing N.sup.2 SYnapse Processors (SYPs), Level 5 containing multiple folded Communicating Adder Tree structures (SCATs), Level 4 made up of N completely connected Neuron Execution Processors (NEPs), Level 3 made up of multiple Programmable Communicating Alu Tree (PCATs) structures, similar to Level 5 SCATs but with programmable function capabilities in each tree node, Level 2 containing the Neuron Instruction Processor (NIP), and Level 1 comprising the Host and user interface. The simplest processors are in the base level with each layer of processors increasing in computational power up to a general purpose host computer acting as the user interface. PLAN is scalable in direct neural network emulation and in virtual processing capability.

Abstract: A cache storage system having hardware for in-cache execution of storage-storage and storage-immediate instructions thereby obviating the need for data to be moved from the cache to a separate execution unit and back to cache.

Abstract: A GVT-NET apparatus for all processor nodes of a parallel system for repetitive calculation of the latest global virtual time (GVT) value quickly and accurately over the communication multi-stage network (NET) that normally transmits data between nodes as point-to-point communications, broadcast, multi-cast, or multi-sender transfers. For multi-processor synchronization, each processing node can free-run and keep track of its local time and synchronize with the other processors by polling all processors to determine the minimal of the individual local times and indicate how far the entire job has progressed. The multi-sender and multi-cast functions in the multi-stage network enable every node attached to the multi-stage network to participate in one common and simultaneous GVT calculation, where each processor node can simultaneously transmit the inverse of its local time to the network and at the same time monitor the network output.

Abstract: The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture for a Scalable Neural Array Process (SNAP) which uses a unique interconnection and communication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. The array processor is made up of multiple sets of orthogonal interconnections and activity generators. Each activity generator is responsive to an output signal in order to generate a neuron value.