Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

Abstract: A DC offset cancellation circuit receives two input signals. A first one of the input signals is amplified by an amplifier, and the amplified output signal of the amplifier is tracked and held during a first clock phase. Simultaneously, during the first clock phase, the second one of the input signals is tracked and held. During the second clock phase succeeding the first clock phase, the stored second one of the input signals is amplified by the same amplifier that was used to amplify the first one of the input signals. The amplified and stored first one of the input signals and the amplified second one of the input signals are summed during the second clock phase to remove any DC offset. The summed signals are sampled and held during the second clock phase. The offset of the summer circuit can be canceled by sequential digital processing.

Abstract: A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge circuit coupled to a primary node, a first device coupled between the primary node and a first secondary node, and a second device coupled between the first secondary node and a second secondary node. A second pre-charge circuit is coupled to the first secondary node and a pre-discharge circuit is coupled to the second secondary node. In response to a first clock polarity, the primary and the second pre-charge circuits pre-charge the primary and the first secondary nodes, respectively, and the pre-discharge circuit pre-discharges the second secondary node. Thereafter, in response to a second clock polarity, the first device creates a path between the primary node and the first secondary node. Because both nodes are pre-charged to the same voltage, charge sharing is substantially prevented.

Abstract: A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.

Abstract: Oxygen implantation can be used to form a buried oxide layer in a substrate. A dielectric masking material is used to shape the buried oxide layer by changing the depth at which ions can implant based on the shape of the dielectric masking layer.

Abstract: The present invention is a complementary active pixel sensor cell and method of making and using the same. The complementary active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a complementary active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and complementary PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract: A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

Abstract: A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

Abstract: A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.

Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Abstract: An H-driver circuit is provided that has a mechanism for selectively reducing one or more RC time constants within the H-driver circuit. Selectively reducing one or more RC time constants within the H-driver circuit reduces the turn-ON time of one or more of the H-driver circuit's pull-up transistors, and increases the speed of the H-driver circuit with little increase in power consumption. Each RC time constant preferably is selectively reduced via a feedback path between an output terminal of the H-driver circuit and a resistance reducer operatively coupled to the pull-up transistor whose turn-ON time is to be reduced. Preferably the resistance reducer comprises a transistor, more preferably a MOSFET and most preferably a p-channel MOSFET.

Abstract: A method and system for transferring data between a processor and a device residing at a non-cacheable address. The method includes the steps of asserting the non-cacheable address onto an address bus, asserting a first signal indicating that the processor has data ready for burst mode transfer between the processor and a device residing at the non-cacheable address, asserting a second signal indicating that the device is ready for the burst mode transfer, and performing a burst mode transfer of a plurality of bytes between the processor and the non-cacheable address. The method of the invention provides both sequential and non-sequential burst transfer modes. The system of the invention provides a processor, a device, bus control logic, and non-cacheable address logic.

Abstract: A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.

Abstract: A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: An apparatus for providing a varying impedance point in a circuit corresponding to a frequency of an input signal applied to the apparatus. Device sizes of the apparatus can be selected to provide varying impedance for desired frequency ranges.

Abstract: A pre-driver circuit in an I/O circuit for an integrated circuit performs the combined functions of voltage level shifting, slew rate control, and tri-state capability, in a single circuit to avoid additional delay caused by implementing any combination of these functions in two or more circuits.

Abstract: The present invention is directed to a method of manufacturing an integrated circuit with two or more gate oxide thicknesses on the same wafer. The method includes the steps of growing a first oxide layer on a substrate, depositing a first polysilicon layer over the first oxide layer, applying a block mask, etching the first polysilicon layer, stripping the block mask, stripping the first oxide layer from the areas opened by the block mask, growing a second oxide layer, depositing a second polysilicon layer, and polishing the second polysilicon layer to remove the second polysilicon layer from everywhere except the areas opened by the block mask. If desired, a polish stop layer may be deposited after depositing the first polysilicon layer. Threshold implants may also be made after the block mask is stripped. Finally, polysilicon shapes may be added to the boundary areas opened by the block mask to help eliminate foreign material problems.

Abstract: A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.