Abstract: A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entry signals intent to use the bus.A microprocessor having two on-board clock generators. The faster clock generator controls the microprocessor during normal, synchronous mode. The slower clock generator controls the microprocessor when the bus must be accessed, or during "snoop" mode which is invoked when another entity signals intent to use the bus.

Abstract: Two controlled current gate drives are provided for driving parallel P and N channel pass devices, so that the rise time of the voltage at one gate of the pass devices overlaps with the fall time of the other to reduce capacitive signal coupling of the signal applied to an FET gate to the FET source and drain. Low-level current sources drive the gates of the pass devices with opposite polarities. A current mirror is used to control the currents provided by the gate drives to control the tradeoff between switching speed and switching noise coupling.

Abstract: A triangular scalable neural array processor unit for use in a neural network has an array of weight registers, multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to input multipliers of selected neurons. The communicating adder trees provide the selectable feedback path.

Abstract: A data processing system gives an application running on the operating system exclusive ownership of a hardware device. The system is operable in two modes. In the first mode the application interacts with the hardware device by making use of the processing system. In this mode many layers of the processing system are involved and the interaction time with the hardware is slow and inconsistent. In the second mode, exclusive ownership of the hardware device is granted to the application by the driver. In this mode the application has direct access to the hardware device thus avoiding the involvement of the processing system layers. The application accesses and uses the driver through a low latency processor interface linked into the application program itself.

Abstract: An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).

Abstract: A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells.

Abstract: Linear and decision feedback equalizers which are communication receivers used in computer systems having an ISI receiver system and analysis paradigm to provide the ability of estimating the performance of these receivers under mismatched channel conditions. The mean square error (MSE) performance of linear and decision feedback equalizers in the presence of arbitrary channel mismatch is presented. A generic equalizer which has feed-forward and feedback taps which are optimized for a mean square error (MSE) criterion. The ability to rapidly predict MSE performance also leads to the real-time adaptation of the equalizer complexity to improve MSE performance, optimal truncation of channel impulse response based on an MSE criterion, and assessing the impact of assuming white noise in a colored noise environment. With the system and method there is a determination of the spectral characteristics of the communication channel during training and/or decoding.

Abstract: A blind hole extending from upper or surface wiring of a printed circuit board to inner or lower wiring, and having an opening larger than the bottom, is formed on a substrate, and a conductor pattern is formed on the bottom and the internal wall of the blind hole to connect the inner wiring with the surface wiring.

Abstract: A triangular scalable neural array processor unit for use in a neural network and having multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to input multipliers of selected neurons.

Abstract: A signal detector circuit in a data receiver including a programmable hysteresis circuit for setting and detecting the presence of both a threshold minimum data signal level and a reset signal level higher than the minimum signal level.

Abstract: A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits.

Abstract: A modularly expandable switch-based planar apparatus for insertable multiple bus-based processor cards and/or expansion cards and interconnecting the cards via a multi-stage switch network which resides on the planar apparatus. The cards require no modification or change of any kind, since the connection to the planar apparatus is made as if the planar apparatus contained the standard MicroChannel interconnection. The planar apparatus implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.

Abstract: A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.

Abstract: A serial communication interface for sending and receiving serial data is provided including a serializer and a deserializer.The serializer is designed so that the serializer VCO has a center frequency that is one half the center frequency of the deserializer VCO. The serializer uses both edges of the clock to mix the serial bits. The deserializer design is unchanged. The two VCO's are implemented on separate chips with both chips located on the same metallized ceramic substrate with a ground plane about 40 mm apart. Near frequency interaction is significantly reduced.

Abstract: A monolithic magnetic device having a plurality of transformer elements having single turn primaries and single turn secondaries fabricated on a plate of ferrite which has the outline of a ceramic leadless chip carrier. Each of the magnetic elements has a primary winding formed from a copper via plated on the ferrite. Each element's secondary is another copper via plated over an insulating layer formed over the first layer of copper. The elements' primaries are interconnected on the first copper layer and the elements' secondaries are interconnected on the second copper layer. The configuration and turns ratio of the transformer are determined by the series and or parallel interconnections of the primary and secondaries. Some of the interconnections can be provided by the next higher assembly level through the circuit card, with the same magnetic device providing many turns ratio combinations or values of inductors.

Abstract: A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells.

Abstract: A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation.

Abstract: Methods and apparatus are set forth for automatically controlling a battery back-up unit (BBU) associated with a rack mounted device, under rack A.C. power outage, rack Emergency Power Off (EPO) and normal rack power down conditions. The methods and apparatus contemplated by the invention deactivate the device BBU whenever either a rack Emergency Power Off (EPO) or normal rack power down condition exists so that BBU power is not unnecessarily drained. The invention features the ability to perform the aforestated device BBU control function without having to redesign a rack enclosure, and without having to use or generate rack signals other than "non-specific" signals, defined as signals that are being generated and used for purposes other than device level BBU switching in a commercially available rack enclosure.