Abstract: A method and apparatus for handling an electrostatic discharge (ESD) pulse in silicon on insulator (SOI) integrated circuits is provided. An ESD pulse is conducted via an ESD protection circuit from a pad to a rail or node. A discriminator means coupled to the rail or node determines when an ESD pulse has occurred and generates a signal in response thereto. The signal from the discriminator means is applied to a body bias circuit.

Abstract: True and complement data signals are provided to a multiplexer, which selects one of them based on a selection signal for capture by a single scannable latch in response to a clock signal. The scannable latch then provides the captured signal for testing by testing logic.

Abstract: The invention comprises an input/output circuit of an integrated circuit chip that includes a pad, a protection circuit connected to the pad, and an up-shift circuit connected to the pad and the protection circuit. The up-shift circuit provides a DC bias voltage to signals received by the pad to protect the protection circuit. With the invention, the protection circuit includes only single gate-oxide devices.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.

Abstract: A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate.

Abstract: A pair of dynamic random access memory cells having each end of the active area surrounded on three sides by a gate conductor. The width of each end of the active area that is surrounded by a gate conductor preferably is less than fifty percent of the width of the deep trench intersected by that end of the active area.

Abstract: The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Abstract: An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Abstract: A device, having circuits formed thereon, comprises a circuit including a frequency generator for generating a detectable radio frequency energy when powered and a power generator, coupled to the frequency generator, for generating power when exposed to light.

Abstract: A method of making a self-aligned dynamic threshold field effect device having a dynamic threshold voltage includes depositing a mandrel layer on the surface of an SOI substrate, then etching a gate opening in the mandrel layer. The gate opening is narrowed by depositing spacer material and a highly doped region, forming a low resistance body region, is created by ion implantation. The narrowed gate opening prevents the low resistance body from connecting the source/drain regions to be formed on opposite sides of the gate-structure. A gate is formed by depositing a dielectric layer in the gate opening, and adding a layer of gate material, then chemical-mechanical polishing to the level of the mandrel layer, then removing the mandrel layer. Conventional processing is then used to create source/drain diffusion regions. The gate is connected to the body by creating a contact region at one end of the gate. The invention includes the device made by the method.

Abstract: A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.

Abstract: A method and apparatus for contact testing a plurality of devices under test, either sequentially or simultaneously. In a first test phase it is determined whether the test probe to each contact is shorted to the most negative rail. In a second phase it is determined whether the test probe has made proper contact, and whether ESD diodes on the devices under test are functional. In both test phases a negative pulse is generated on a tester bus and applied to the contact by the test probe. In the first test phase the positive rail of the device under test is grounded; in the second test phase the positive rail of the device under test is made positive. The negative rail of the device under test is connected to the negative rail of the tester. In both test phases, upon termination of the negative pulse, the bus is restored to a positive voltage which is dependent upon the condition of the contact and the condition of expected input devises at the contact.

Abstract: A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

Abstract: A body contact to a SOI device is created by providing a deeper buried oxide region for providing connection to the FET body.

Abstract: A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.

Abstract: A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting.

Abstract: A testing device for slowly bleeding charge away from a primary node in a dynamic logic circuit. A properly functioning keeper device in the dynamic logic circuit will maintain the primary node in a precharged state even in the face of this bleeding device. If the logic circuit output flips after the bleeder device begins bleeding charge, a defective keeper device is thereby identified.

Abstract: The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.