Abstract: A digital power monitoring circuit for monitoring power through an output inductor of a switching power supply in accordance with an embodiment of the present application includes a first analog to digital converter receiving a current sense signal indicative of the current through the output inductor and providing a first digital signal including information regarding the current through the output inductor, a second analog to digital converter receiving a signal indicative of the output voltage of the switching power supply and providing a second digital signal containing information regarding the output voltage of the switching power supply; and a convolver circuit operable to receive the first digital signal and the second digital signal and to provide a third digital signal including information regarding the power through the output inductor based on the first and second digital signals.

Abstract: There is disclosed a system and method for providing location-based entertainment. In one embodiment, a device capable of providing location-based entertainment comprises a navigational interface module configured to receive navigational data, an entertainment selection module configured to utilize the navigational data to generate location-based entertainment content for a user, and a presentation module configured to present the location-based content to the user. The system may also include a position finding module and a routing module.

Abstract: Methods and systems for intra-printed circuit board communication via waveguides are disclosed and may include communicating one or more signals between or among a plurality of integrated circuits via one or more waveguides integrated on a printed circuit board. The integrated circuits may be bonded to the printed circuit board. The waveguides may be configured via switches integrated within each of the plurality of integrated circuits. The one or more signals may include microwave signals. The one or more waveguides may be configured for communicating microwave signals with a frequency of 60 GHz or greater. The communication of the one or more signals may be configured via a low frequency control signal, which may include a digital signal. The one or more waveguides may include metal and/or semiconductor layers deposited on and/or embedded within the printed circuit board.

Abstract: A discharge sustain driver circuit for a plasma display device, the driver circuit comprising a first transistor switching circuit for switching a DC bus voltage across the plasma display device; a storage capacitance; at least one inductor; and first and second bi-directional switching circuits coupled in series and being coupled to the first switching circuit to transfer charge from the plasma display device through the at least one inductor to the storage capacitance, and back to the plasma display device; and a controller for the bi-directional switching circuits to control the bi-directional switching circuits so as to receive the charge on the storage capacitance and return the charge in an opposite charge direction to the plasma display device.

Abstract: According to one exemplary embodiment, a method for robust statistical semiconductor device modeling includes building a semiconductor device model using at least one new device parameter variation, constructing a variation library for the semiconductor device model, and verifying the variation library against measured data from physical semiconductor devices. The variation library is constructed by determining variations of the at least one new device parameter variation and standard device parameters as functions of, for example. sizes and locations of semiconductor devices on semiconductor dies.

Abstract: A method for processing signals in a communication system includes delaying a baseband signal based on at least one calibration signal, and amplifying the delayed baseband signal. The at least one calibration signal may be generated based on an amount of intermodulation distortion associated with the amplified delayed baseband signal. A bias voltage of an amplifier used for the amplifying may be adjusted, where the adjusting is in proportion to an envelope of the baseband signal. A number of samples used for the delaying may be calculated, by minimizing the amount of the intermodulation distortion at an output of the amplifier. The envelope may be measured by evaluating a plurality of I and Q samples of the baseband signal. A supply and/or bias voltage for the amplifier may be generated by using a switching regulator. The bias voltage may control a gain of the amplifier.

Abstract: Aspects of a method and system for a transformer in an integrated circuit package are provided. In this regard, signals may be transmitted and/or received via an antenna communicatively coupled to a transformer embedded in multi-layer integrated circuit package. The windings ratio of the transformer may be configured based on an impedance of the antenna, an impedance of a transmitter coupled to the transformer, an impedance of an LNA coupled to the transformer, and/or a power level of the received and/or transmitted signals. The windings ratio may be configured via one or more switching elements which may be MEMS switches embedded in the multi-layer IC package. The transformer may comprise a plurality of loops fabricated on a corresponding plurality of metal layers in the multi-layer IC package, and the loops may be communicatively coupled with one or more vias. The multi-layer IC package may comprise ferromagnetic and/or ferromagnetic materials.

Abstract: Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode.

Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

Abstract: A charge circuit for providing a gate driver supply voltage for a gate driver of a switching power supply in accordance with an embodiment of the present application includes a first voltage source providing a first voltage and a charge pump circuit connected to the first voltage source and operable to be turned ON and OFF to improve efficiency such that an increased output voltage of the charge circuit is provided when the charge pump circuit is ON, and wherein the output voltage is the gate driver supply voltage.

Abstract: A torsionally elastic clutch is provided including a primary part and a secondary part connected to transfer torque, and including an elastic connecting member having a first attachment surface placed externally in the radial direction of the clutch, and a second attachment surface placed internally in the radial direction of the clutch, connected to transfer torque with the primary part and the other with the secondary part, the two attachment surfaces are displaced relative to each other in the axial direction of the clutch, and further including a tensioning device, which maintains the relative displacement of the two attachment surfaces. An axial bearing is provided between the primary part and the secondary part, which permits a relative twisting in the circumferential direction of the clutch between the primary part and the secondary part, and additionally the tensioning device applies a compressive stress to the axial bearing.

Abstract: Methods and systems for inter-chip communication via integrated circuit package waveguides are disclosed and may include communicating one or more signals between or among a plurality of integrated circuits via one or more waveguides integrated in a multi-layer package. The integrated circuits may be bonded to the multi-layer package. The waveguides may be configured via switches in the integrated circuits or by MEMS switches integrated in the multi-layer package. The signals may include a microwave signal and a low frequency control signal that may configure the microwave signal. The low frequency control signal may include a digital signal. The waveguides may comprise metal and/or semiconductor layers deposited on and/or embedded within the multi-layer package.

Abstract: The present invention discloses a method for indicating a modulation mode in HSDPA, comprising the following steps: a NodeB receiving capability information reported by a terminal, if determining that the terminal supports 64QAM modulation mode, determining a transmission block size, a modulation mode and code channel resource to be indicated based on an capability constraint condition and the capability information, and if the determined modulation mode is the same as a basic modulation mode satisfying requirement of the transmission block size, setting modulation mode information of a HS-SCCH as 0, otherwise setting the modulation mode information of the HS-SCCH as 1, and then sending the HS-SCCH to the terminal. Application of the present invention is compatible with a UE device which supports or does not support 64QAM high order modulation, without changing the current frame structure of the HS-SCCH, thereby achieving functional support of the 64QAM modulation mode.

Abstract: Aspects of a method and system for reducing transceiver power via a variable number of channels are provided. In this regard, utilization and/or availability of network and/or device resources may be determined and a configuration of channels utilized for transmitting data may be determined based on the determined utilization and/or availability of resources. Accordingly, the number of channels over which data is communicated may be altered based on determined thresholds for the utilization and/or availability of resources. Moreover, the configuration of channels utilized for communicating data may be dynamically altered by monitoring changes to the utilization and/or availability of resources. For example, the number of channels may be altered based on available bandwidth on one or more channels, based on capacity and/or available space of one or more buffers, and/or based on available power or desired power consumption of a transmitter.

Abstract: According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Abstract: An interposer electrical interface for placing a DC-DC converter in close proximity with an IC powered by the converter, the DC-DC converter including at least one switching node power supply stage, the at least one switching node power supply stage providing regulated power to the IC, the close proximity of the DC-DC converter and IC allowing for high efficiency in provision of the regulated power from the DC-DC converter to the IC, the interposer electrical interface comprising at least one electrical energy storage element.

Abstract: An active play system and method are provided that allow a piece of content to be transferred between multiple content devices associated with the user.

Abstract: Media content, based on a predetermined set of constraints, from a content provider is delivered to a local cache of a user device before viewing the media. A client asset manager process resides in the user device, an asset list at the content provider site, and the media assets are located at a remote site.

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.