Patents Represented by Attorney Fellers, Snider, et al.
  • Patent number: 8059364
    Abstract: The present invention relates to preformed seals used in the manufacture of low density gas filled disk drives. The seals may be preformed to facilitate positioning in the disk drive and eliminate the need for manually applied or semi-automatically applied epoxies, thereby reducing manual labor costs, non-uniform seals, waste and inefficiencies due to equipment malfunction. The epoxy seals may soften and seal after being positioned, thereby forming an in-place hermetic or substantially hermetic seal.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: November 15, 2011
    Assignee: Maxtor Corporation
    Inventors: Thomas G. Andrikowich, Kimberly C. Mann, Mai X. Nguyen
  • Patent number: 8054678
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Patent number: 8054706
    Abstract: A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Phillip Mark Goldman, Muralikrishnan Balakrishnan
  • Patent number: 8050072
    Abstract: A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Yuan Yan, Brian Lee, Ran Wang
  • Patent number: 8050092
    Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Harry Hongyue Liu, Brian Lee, Yong Lu, Dadi Setiadi
  • Patent number: 8045412
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Patent number: 8045361
    Abstract: A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hyung-Kyu Lee, YoungPil Kim, Chulmin Jung
  • Patent number: 8040713
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • Patent number: 8040743
    Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Hai (Helen) Li, Yong Lu
  • Patent number: 8037934
    Abstract: An apparatus for use in deployment of downhole tools is disclosed. Preferably, the apparatus includes at least an in-ground well casing, a housing providing a hermetically sealed electronics compartment, a tool attachment portion, and a first flow through core. The housing is preferably configured for sliding communication with the well casing. The hermetically sealed electronics compartment secures a processor and a location sensing system, which communicates with the processor while interacting exclusively with features of the well casing to determine the location of the housing within the well casing. A preferred embodiment further includes a well plug affixed to the tool attachment portion, the well plug includes a second flow through core capped with a core plug with a core plug release mechanism, which upon activation provides separation between the second flow through core and the core plug, allowing material to flow through said first and second flow through cores.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: October 18, 2011
    Assignee: Intelligent Tools IP, LLC
    Inventor: Dennis A. Strickland
  • Patent number: 8028732
    Abstract: Preferably, an embodiment of a tire inflation system includes at least an axle housing a pressurized fluid, a hubcap supported by the axle and having an interior and an exterior, and a rotary union axially aligned with the axle and mounted to the hubcap from the exterior of the hubcap. The rotary union preferably includes at least a rotating portion and a non-rotating portion, the rotating portion rotates with hub cap, and the non-rotating portion including at least a fluid conduit defining an air passage there through. The air conduit is preferably in fluid communication with the source of pressurized air, and is preferably configured for conducting pressurized air from said source of pressurized air to a tire mounted to the wheel of the vehicle, and for developing a dynamic seal between the fluid conduit and the rotating portion.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 4, 2011
    Assignee: Airgo IP, LLC
    Inventors: Anthony L. Ingram, Calvin Burgess, Michael H. Penwell, Patrick E. Roberts
  • Patent number: 8024818
    Abstract: Apparatus for shading a user's neck. In some embodiments, a support device comprises a flexible, generally U-shaped structure with a laterally extending central portion to accommodate attachment of a proximal edge of a neckpiece, and opposing leg portions which extend from the central portion to engage the headwear. In further embodiments, the neckpiece preferably comprises a layer of flexible material with a proximal end supported adjacent a headwear and an opposing distal end configured to be suspended adjacent to a base of the user's neck. A support portion is formed from laterally extending first and second panels which fold together to form a V-shaped channel circumferentially extending in contact against an outermost rearward surface of the headwear. A flap portion extending from the second panel is moveable between a deployed state to cover the user's neck to a retracted state in which the flap portion is gathered into the channel.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: September 27, 2011
    Assignee: Davenport Innovations, Inc.
    Inventor: Steven Roy Davenport
  • Patent number: 8014167
    Abstract: A hermetically sealed housing having a base deck, a cover member and a seal assembly constructed of a liquid crystal material (LCM), the base deck and cover member forming an enclosure containing an inert gas atmosphere. Various embodiments have the LCM seal bonded to one or both of the base deck and cover member and bonded to seal the enclosure by molding, compression, adhesive bonding, thermoplastic welding or soldering, or a combination of such.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: September 6, 2011
    Assignee: Seagate Technology LLC
    Inventors: Neal F. Gunderson, Daniel D. Dittmer, Michael A. Mewes
  • Patent number: 8015350
    Abstract: Method and apparatus for using block level quality of service (QOS) data in a data storage device. A memory space is provided with a plurality of physical data storage blocks, such as data sectors on a magnetic disc. The QOS data identify at least one QOS characteristic for each of the available blocks. Transfers of user data between the blocks and a host device are preferably carried out in relation to the QOS data. In some preferred embodiments, the QOS data identifies a certification state for each of the blocks. In this way, the device is manufactured with less than all of the blocks having been successfully certified, and the remaining blocks are certified by the device during field use. In other preferred embodiments, the QOS data include a virus scan status, an access history, a write status, or an overlapped track indication for each said block.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 6, 2011
    Assignee: Seagate Technology LLC
    Inventors: Timothy R. Feldman, Jonathan W. Haines, William B. Raspotnik, Craig W. Miller, Edwin Scott Olds
  • Patent number: 8013762
    Abstract: Method and apparatus for compressing data. In accordance with various embodiments, an input string of data bits is received and arranged into fixed-sized chunks. Multiple successive chunks of the input string are compared to previously received chunks of the input string during a single clock cycle. At least two alternative encoding solutions are identified based on matches obtained during said comparison. The input string is compressed to form a compressed output string using a selected one of the at least two alternative encoding solutions that achieves a fewer number of bits in said output string.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: September 6, 2011
    Assignee: Seagate Technology LLC
    Inventors: Donald Preston Matthews, Jr., David Orrin Sluiter
  • Patent number: 8009457
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
  • Patent number: 8009458
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Patent number: 8004875
    Abstract: A data storage device and associated method for providing current magnitude compensation for memory cells in a data storage array. In accordance with some embodiments, unit cells are connected between spaced apart first and second control lines of common length. An equalization circuit is configured to respectively apply a common current magnitude through each of the unit cells by adjusting a voltage applied to the cells in relation to a location of each of the cells along the first and second control lines.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Markus Jan Peter Siegert, Michael Xuefei Tang, Andrew John Carter, Alan Xuguang Wang
  • Patent number: 8004872
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Patent number: 7999337
    Abstract: Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: August 16, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Haiwen Xi, Michael Xuefei Tang