Patents Represented by Attorney Fellers, Snider, et al.
  • Patent number: 7944731
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Patent number: 7944729
    Abstract: Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: May 17, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • Patent number: 7940592
    Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 10, 2011
    Assignee: Seagate Technology LLC
    Inventors: Daniel Seymour Reed, Yon Lu, Song S. Xue, Dimitar V. Dimitrov, Paul E. Anderson
  • Patent number: 7936597
    Abstract: The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Thomas W. Clinton, Michael A. Seigler, Mark W. Convington, Werner Scholz
  • Patent number: 7936629
    Abstract: Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Andrew J. Carter, Maroun Khoury, Yong Lu, Yiran Chen
  • Patent number: 7936625
    Abstract: Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, KangYong Kim, Henry F. Huang
  • Patent number: 7936057
    Abstract: Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dadi Setiadi, Patrick Ryan
  • Patent number: 7936585
    Abstract: A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Wei Tian, Insik Jin, Venugopalan Vaithyanathan, Haiwen Xi, Michael Xuefei Tang, Brian Lee
  • Patent number: 7936622
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Dadi Setiadi, Harry Hongyue Liu, Brian Lee
  • Patent number: 7933136
    Abstract: A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 26, 2011
    Assignee: Seagate Technology LLC
    Inventors: Andrew John Carter, Maroun Georges Khoury, Yong Lu, Roger Glenn Rolbiecki
  • Patent number: 7922691
    Abstract: An angioplasty device and particle trap for use in removal of a particle from a small diameter vessel or vessel-like structure is disclosed. One embodiment includes a catheter for insertion into a vessel-like structure, the catheter having a catheter wall and a movable member, a trap operably connected to the catheter wall and to the movable member, wherein relative motion between the catheter wall and the movable member actuates the trap. In one embodiment, the expanded trap is formed from struts in a spiral-shaped configuration. In one embodiment, the contracted trap forms a waist to creates a pinch-point to trap particles. In one embodiment, the contracted trap forms a cocoon-like structure to further trap particles. In one embodiment, the angioplasty device includes a handle to actuate the trap from a contracted position to an expanded position and return to a contracted position. The handle provides rotational or longitudinal or both types of movement to actuate the trap.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: April 12, 2011
    Assignee: Kletschka Foundation
    Inventors: Harold D. Kletschka, Brian Packard
  • Patent number: 7922586
    Abstract: A system featuring a server communicating with the network with game hosting software programmed on the server, a terrain database and a time sequence GPS position linked message database each stored on the server and accessed by the game hosting software is disclosed. The terrain database stores a plurality of three dimensional renderings of golf courses created from digital aerial photographs of each golf course, wherein each photo includes elevational and slope data for each aerial photo. The time sequence GPS position linked message database contains a plurality of messages collected by a portable computing device and transmitted to the server by the device during an actually played round of golf. Each message is: transmitted by the device to the server; associated with an elapsed time from the beginning of the play of the round of golf, and linked to a GPS determined position from where the message was transmitted.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 12, 2011
    Inventors: Francis Aicher Heckendorf, III, Mathew N. Matelan
  • Patent number: 7922245
    Abstract: A portable table and seating combination is disclosed. The combination includes at least a first portion of a hinge attached to a tabletop portion. The tabletop portion includes at least a top surface, and a plurality of edge portions extending from the top surface. The top surface in combination with the plurality of edge portions forms a seating confinement compartment. The combination further includes at least a retractable leg support attached to the tabletop portion. The retractable leg support resides adjacent the seating confinement compartment, and in an extended position the retractable leg support, supports the tabletop portion at a predetermined distance above a surface. The combination also includes at least a seating portion configured for confinement within the seating confinement compartment. In a first embodiment, the seating portion is an integrated seating portion. In an alternate embodiment, the seating portion is a freestanding seating portion.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: April 12, 2011
    Inventor: Ravi K. Sawhney
  • Patent number: 7916528
    Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
  • Patent number: 7917906
    Abstract: Method and apparatus for allocating system resources for use by software processes in a computer-based system, such as a wide area network (WAN) comprising a data storage array. A first memory space provides a first bit indicator to indicate whether at least one system resource is available for use. A second memory space provides a second bit indicator to indicate whether a pending software process awaits availability of the system resource. The resource is allocated for use by the process in relation to a combinatorial operation upon the first and second bit indicators, preferably comprising a logical AND operation. The first and second memory spaces are preferably characterized as multi-bit registers. A free resource stack identifies available resources, and a process queue identifies pending processes waiting for released processes. The statuses of the respective stack and queue are reflected in the bits in the multi-bit registers.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventor: Michael D. Walker
  • Patent number: 7914423
    Abstract: An athletic striking apparatus that includes at least an impact member supported by a base. The preferred embodiment further includes a plurality of predetermined angular settings provided by the base. The impact member preferably oscillates in one of at least two distinct predetermined frequencies. In accordance with the preferred embodiments, a method of using an athletic striking apparatus that includes at least the steps of providing an impact member supported by a base. A step of striking the impact member supported by the base preferably follows the providing step. The base further preferably provides a plurality of predetermined angular settings for the impact member. Also in an alternative preferred embodiment, the impact member oscillates in at least two distinct predetermined frequencies in response to an impact.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: March 29, 2011
    Inventor: Michael P. Cogan
  • Patent number: 7914858
    Abstract: A method and apparatus for sealing disk drive housing castings and the resulting housings. A housing component of a data storage device is placed in an environment of decreased pressure where a first tank that is an autoclave is pressurized at a selected pressure and the environment is a first tank that encloses the housing component. A second tank that is an autoclave is pressurized at substantially the same pressure as the first tank while the second tank is fluidically coupled to the first tank and encloses a sealant. The sealant is applied to a surface of the component when it is under decreased pressure by transferring the sealant from the first tank to the second tank. A pressure of at least one atmosphere is further applied so that a portion of the sealant contactingly permeates voids in the housing component before the sealant is subsequently cured.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: March 29, 2011
    Assignee: Maxtor Corporation
    Inventors: Charles deJesus, Thomas G. Andrikowich, Michael C. Strzepa
  • Patent number: 7916515
    Abstract: An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Alan Xuguang Wang
  • Patent number: 7911733
    Abstract: The present invention provides a multilayer tape for simultaneously providing shielding of electromagnetic interference (EMI) and evidence of tampering with an electronic device to which it is applied. The multilayer tape can be attached to an electronic device to cover a seam or other opening in the electronic device. An embossed surface provides evidence of the disruption of the tape, and the tape includes a conductive adhesive to provide EMI shielding. The multilayer tape is particularly useful for sealing the seams of a disk drive device.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: March 22, 2011
    Assignee: Seagate Technology LLC
    Inventor: John S. Deeken
  • Patent number: 7913038
    Abstract: A data storage apparatus and associated method is provided wherein a software system is resident in a memory space and is configured to encode data retrieved from a first number of logical units into a single channel in order to store the data in a second number of logical units.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: March 22, 2011
    Assignee: Seagate Technology LLC
    Inventor: Stephen J. Sicola