Abstract: An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.

Abstract: A parallel plate beam forming lens is formed form at least three parallel plates, and includes a plurality of beam port waveguides, each coupled to a beam port divider with a step increase in waveguide height. The beam port divider comprises a first divider having two outputs separated by a resistive septum, each of which is coupled to a second divider having two outputs separated by a resistive septum, with all of the second divider outputs coupled to a lens region through beam port apertures. On the opposite end from the beam port waveguides is a plurality of array port waveguides forming a transformer, thereafter to a section of waveguide, and thereafter to an array port divider including a resistive septum coupled to the lens region and a step decrease in waveguide height. Also positioned at the extents of the beam port apertures and the array port apertures are a plurality of dummy ports.

Abstract: An apparatus for the formation of a dense plasma focus (DPF) has a center electrode formed about an axis, where the center electrode includes a cylindrical part and a tapered part. An outer electrode is formed about the center electrode, and may be either cylindrical, tapered, or formed from a plurality of individual conductors including a helical conductor arrangement surrounding the tapered region of the center conductor. The taper of the center electrode results in an enhanced azimuthal B field in the final region of the device, resulting in increased plasma velocity prior to the dense plasma focus. Using the outer electrode helical structure an auxiliary axial B field is generated during the final acceleration region of the plasma, which reduces axial modal tearing of the plasma in the final acceleration region.

Abstract: An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, the interrupt controller has, for a second thread, an interrupt request register accessible to the first thread, an interrupt count accessible to the first thread, and an interrupt acknowledge accessible to the second thread. Each interrupt controller separately has a counter for each request which increments upon assertion of a request and decrements upon assertion of an acknowledgement.

Abstract: A wireless signal processor includes an analog front end for generating at least one baseband analog signal, at least one analog to digital converter for converting the baseband signal into a digital signal, the analog to digital converter having a resolution width and a sampling rate, and a baseband processor for measuring the signal energy in the analog to digital converter output, and when the incoming signal energy level increases or a baseband processor detects a packet, at least one of the sampling rate or resolution width also increases until the end of the packet, after which the sample rate and resolution are reduced to an interpacket rate and resolution. Additionally, the sampling rate and resolution increase after packet detection at rates and resolutions which are dependent on packet type and data rate.

Abstract: A SINR estimator receiving a symbol stream has a delay element coupled to the symbol stream to produce a delayed symbol stream, which is also coupled to a conjugator. A first multiplier forms a product from the symbol stream and the output of the conjugator, thereafter summing these values over an interval L and scaling by L to form a correlated power estimate Cn. A second multiplier forms a product from the symbol stream which is multiplied by the conjugate of the input, thereafter summing these values over the preamble interval 2L and scaling by 2L to form a non-correlated power estimate Pn. Cn and Pn are compared to generate an SINR estimate.

Abstract: A wireless link simulator includes, in sequence, a digital transmit device under test (TX-DUT), a wireless link simulator, and a digital receive device under test (RX-DUT). The wireless link simulator includes, in sequence, a transmitter IQ imbalance generator, a power amplifier non-linearity generator, a noise floor generator, a multi-path channel generator, a receive noise generator, a frequency offset generator, a phase noise generator, a receive IQ imbalance generator, and a DC offset generator. Each of the generators may be individually varied to determine the receiver sensitivity to each of these effects and associated parameters.

Abstract: A maximum likelihood CCK detector has a first subtractor which subtracts the contents of a pre-equalize register from a current symbol, and the output of this subtractor is coupled to a simple Fast Walsh Transform (FWT) with an iteration variable k. The output of the FWT is coupled to a second subtractor for subtracting a plurality of ICI corrections for all possible current symbols computed from the post-FWT domain value of the current CCK symbol and stored in post equalization registers. A post equalization register contains values computed from feedback filter coefficients determined during a packet preamble, where the feedback filter coefficients are provided to a reduced complexity post equalization value generator which populates the post equalization register using an iteration variable i.

Abstract: During the preamble interval of a wireless packet, a receiver estimates the SINR of the preamble, and also examines the packet header to determine the data rate, length, and destination address. If the SINR as determined from the preamble is below a threshold, or if the SINR combined with the data rate from the packet header is below a threshold, the receiver is powered down for the duration of the current packet. Additionally, if the packet header bears a destination address for a different station from the one receiving it, the receiver is powered down for the duration of the packet. In this manner, the receiver power is only used to receive packets that have sufficient SINR to be correctly received for their data rate, or are destined for the present station. The reduction in power consumption results in longer battery life for the station.

Abstract: A high speed communications interface divides data into a plurality of lanes, each lane encoded with clocking information, serialized, and sent to an interface. During cycles when there is no available data to send, IDLE_EVEN and IDLE_ODD cells are sent on alternating cycles. Data is transmitted by sending a header which spans all lanes and includes a START symbol. The final data transaction includes a Frame Check Sequence (FCS) which operates over the entire header and data. The packet is terminated by an END symbol, which is sent after the final data, and the remainder of the lanes are padded with IDLE_EVEN, IDLE_ODD, IDLE_EVEN_BUSY, or IDLE_ODD_BUSY cycles. The interface has a variable clock rate.

Abstract: A porous cathode structure is fabricated from a plurality of wires which are placed in proximity to each other in elevated temperature and pressure for a sintering time. The sintering process produces the porous cathode structure which may be divided into a plurality of individual porous cathodes, one of which may be placed into a dispenser cathode support which includes a cavity for containing a work function reduction material such as BaO, CaO, and Al2O3. The work function reduction material migrates through the pores of the porous cathode from a work replenishment surface adjacent to the cavity of the dispenser cathode support to an emitting cathode surface, thereby providing a dispenser cathode which has a uniform work function and therefore a uniform electron emission.

Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: A plasma thruster with a cylindrical inner and cylindrical outer electrode generates plasma particles from the application of energy stored in an inductor to a surface suitable for the formation of a plasma and expansion of plasma particles. The plasma production results in the generation of charged particles suitable for generating a reaction force, and the charged particles are guided by a magnetic field produced by the same inductor used to store the energy used to form the plasma.

Abstract: Integrated fiber tap monitors with variable optical attenuators where light from an input fiber is reflected to the output fiber and a tap is generated from measuring transmission at the reflection.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digital output and a plurality of digital control and status signals and to a receive processor having a digital input and a plurality of digital control and status signals by multiplexing analog to digital converters and digital to analog converters such that during a receive time the converters are used for a receive purpose and during a transmit time, the converters are used for a transmit purpose.

Abstract: A process and apparatus for water purification has a stationary electrode opposing a movable electrode which are positioned about a passageway for the water to be purified. The stationary electrode and movable electrode form an arc gap, and the arc gap is fed with a voltage from a pulsatile power supply. The arc gap is reduced when the current is below a first threshold and increased when the current is above a second threshold, and the arc gap change is realized by controlling a motor attached to feeder rollers coupled to the movable electrode. The apparatus causes the formation of oxide nano-particles providing durable bactericidal action.

Abstract: A plasma generator for three phase mains alternating current operation has three plasma generation tubes interconnected with a nozzle, each plasma generation tube having a plasma initiator for forming a plasma into an electrode ring, the electrode ring including substantially tangential gas introduction orifices which cause gas entering the electrode ring to helically rotate. Each of the electrode rings is coupled to a unique one of the three phases of AC voltage supply, such that when the initiator plasma is introduced into one of the electrode rings, a plasma discharge occurs with a path from the electrode ring, through the plasma generation tube, and to a different electrode ring.

Abstract: An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.