Abstract: A programmable logic fabric includes configurable logic block (CLB) containing registers and combinatorial logic elements. An input switch matrix distributes incoming signals to CLB inputs or inputs of embedded logic elements including a register clock. A routing network allows a variety of routing paths with distinct delays to be selected to route the CLB outputs to the input switch matrices. Presented clock delay insertion architectures allow a leaf node of dedicated clock network and a register clock input can be alternatively routed through the routing network, thereby allowing for the generation of a variable amount of clock delay. Required clock delay for each register minimizing the clock period is computed by clock skew optimization program. A set of alternative clock routes is generated for each register clock where each route delay is close to the corresponding required delay while satisfying the monotone increasing conditions.

Abstract: Integrated fiber tap monitors with variable optical attenuators where light from an input fiber is reflected to the output fiber and a tap is generated from measuring transmission at the reflection.

Abstract: A plurality of high atomic number wires are sintered together to form a porous rod that is parted into porous disks which will be used as x-ray targets. A thermally conductive material is introduced into the pores of the rod, and when a stream of electrons impinges on the sintered wire target and generates x-rays, the heat generated by the impinging x-rays is removed by the thermally conductive material interspersed in the pores of the wires.

Abstract: A decision processor for 802.11b codewords for 1 Mb and 2 Mb data rates includes a sliding correlator for the acquisition of correlation peaks. During a training interval, these correlation peaks are summed into a channel profile memory. The correlation peaks corresponding to a codeword are added into the channel profile memory, and correlation peaks corresponding to the inverse of this codeword are inverted and added into the channel profile memory during the training interval. After the training interval, a decision interval follows whereby correlation peaks are multiplied by the complex conjugate of the contents of the channel profile memory. The multiplication results are accumulated over a codeword window interval to produce a decision output.

Abstract: A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data.

Abstract: An apparatus for providing power to a gas discharge lamp comprises a storage capacitor and an ignition switch coupled through a primarily parasitic first inductor to a parallel combination of a diode assembly and a second inductor in series with a gas discharge lamp. The second inductor is selected to optimize the energy transfer from the capacitor to the gas discharge lamp. During a first interval determined by the time constant of the series combination of a storage capacitor, a first inductor, and a second inductor, the diode assembly is not conducting and a forward sense current builds in the first and second inductors.

Abstract: A tunable optical fiber has a grating which is attached to an expander responsive to an external control including a temperature or a magnetic field. The expander changes length, and this is coupled to the optical fiber, which changes pitch, thereby accomplishing a tuning change. The expander may be coupled to the grating directly, or through an expansion reducer, which produces a greater range of tuning. Terfenol-D™ may be used for the expander material, and tubes which include a bonding point adjacent to the extents of the grating may form the extent reducers.

Abstract: A fiber optic sensor system includes a plurality m of sensor segments, each sensor segment further comprising a plurality n of sensor gratings for making measurements. Each sensor grating of the sensor segment operates within a unique wavelength channel, such that a plurality m of sensor segments have m sensors in each wavelength channel, and n wavelength channels, for a total of m*n sensors. A broadband optical source is gated for a duration of time which enables all of the sensors on a sensor segment to reflect optical energy corresponding to their measurement, but not long enough to receive reflected optical energy from more than one sensor on a single wavelenghth channel. In this manner, n wavelength channels of measurement can be time-multiplexed to measure m*n sensors.