Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.
Type:
Grant
Filed:
May 13, 2002
Date of Patent:
August 17, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Sujit Sharan, Howard E. Rhodes, Philip J. Ireland, Gurtej S. Sandhu
Abstract: A stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a pre-formed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.
Type:
Grant
Filed:
June 2, 2000
Date of Patent:
August 17, 2004
Inventors:
Todd O. Bolken, Cary J. Baerlocher, Chad A. Cobbley, David J. Corisis
Abstract: A method and apparatus for attaching an integrated circuit die to a leadframe or substrate. Specifically, a wafer, which is populated with integrated circuit dies, is electrically tested and a wafer map is generated depicting the electrically good dies. An adhesive material is deposited on only the electrically good dies in accordance with the wafer map. The electrically good integrated circuit die may then be attached to a leadframe or substrate.
Abstract: A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an overlying solder bump or solder ball. Additionally, the tapered contact structure allows the use of either larger contact pads or, alternately, allows a greater density of contact pads to be achieved on an integrated circuit substrate.
Type:
Grant
Filed:
July 11, 2002
Date of Patent:
July 27, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Warren M. Farnworth, Joseph T. Lindgren
Abstract: The illustrated embodiments relate to a control circuit that uses a latency signal to generate an output signal. The latency is used to create a control signal that is dependent on the latency signal. The control signal is used to select from among multiple input sources. The selected input source is used to create an output signal.
Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.
Abstract: The disclosed embodiments relate to an input buffer circuit. The input buffer circuit comprises a first input buffer having a first operational characteristic and a second input buffer having a second operational characteristic. The output of the first input buffer or the second input buffer is selected responsive to buffer selection input data.
Abstract: In a sputtering apparatus, target particles to be deposited onto a substrate are selectively ionized relative to other particles in the deposition chamber. For example, titanium or titanium-containing target particles are selectively ionized, while inert particles, such as argon atoms, remain substantially unaffected. Advantageously, one or more optical ionizers, such as lasers, are used to create one or more ionization zones within the deposition chamber in which such selective ionization takes place.
Abstract: An information management system produces a standard bill of resources based on bills of resources that include a list of resources to be utilized in performing a procedure. The system includes a general purpose computer system with storage means, processing means, display means, and input means. Information management software installed on the general purpose computer includes node software objects providing a health care information management function, including a clinical pathway node software object, a case management node software object, and a standardization review node software object. The clinical pathway node software object creates clinical pathway module software objects, including resource software objects and container software objects.
Type:
Grant
Filed:
December 11, 2000
Date of Patent:
June 22, 2004
Assignee:
GE Medical Systems Information Technologies, Inc.
Inventors:
Brian C. DeBusk, Elizabeth C. DeBusk, Mark W. Shanks, Michael C. Cofer, W. Francis Lukens
Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.
Abstract: Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the process flow to remove or weaken certain layers formed in the wordlines. For instance, an SiNx layer and a crystallized W2N layer may form during the fabrication of the wordline. While the layers may provide certain advantages at certain points in the fabrication process, they may be undesirable at subsequent points. One or more anneal processes may be implemented at various points in the processing to eliminate the crystallized W2N layer and weaken the SiNx layer.
Type:
Grant
Filed:
January 16, 2003
Date of Patent:
May 11, 2004
Inventors:
Yongjun Jeff Hu, Satish Bedge, Kevin Torek
Abstract: A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.
Type:
Grant
Filed:
April 23, 2002
Date of Patent:
May 11, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Stephen L. James, Richard W. Wensel, Brad D. Rumsey
Abstract: A method for converting digitized image pixel values from a first range to a second range including (a) determining a lower limit value of a relevant portion of the first range; (b) generating an intensity histogram representative of pixel populations having specified intensities, and transforming the histogram to generate a log-transformed histogram; (c) identifying a threshold value for an upper limit of log-transformed values from the log-transformed histogram; (d) identifying a population of pixels having log-transformed values having a desired relationship to the threshold value; (e) determining an upper limit value of the relevant portion of the first range based upon the identified population; (f) converting the pixel values to converted values over the second range based upon the lower and upper limit values; and (g) transmitting information relating to an image associated with the pixel values or sources thereof between a first location and a second location remote from the first location to provide
Abstract: A method and apparatus for inducing heat within a workpiece. A flexible fluid-cooled induction heating cable is used to produce a magnetic field to induce electric current in a workpiece. The induction heating cable has separate fluid and electrical connectors to separately couple cooling fluid and electric current to and from the induction heating cable. An induction heating system having a fluid cooling unit, a power source, and a flexible fluid-cooled induction heating cable having separate fluid and electrical connectors. An extension cable may be used to enable the flexible fluid-cooled induction heating cable to be used at a greater distance from the power source and the fluid cooling unit. An insulation blanket adapted for use with a specific size workpiece may be used with the flexible fluid-cooled induction heating cable.
Type:
Grant
Filed:
August 27, 2001
Date of Patent:
April 27, 2004
Assignee:
Illinois Tool Works Inc.
Inventors:
Jeffrey R. Thomas, Randall G. Baxter, Mark A. Ulrich, Paul D. Verhagen
Abstract: A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.