Abstract: A technique for reducing the latency associated with a memory read request. A bypass path is provided to direct the address of a corresponding request to a memory controller. The memory controller initiates a speculative read request to the corresponding address location. In the meantime, the original request is decoded and directed to the targeted area of the system. If the request is a read request, the memory controller will receive the request, and after comparing the request address to the address received via the bypass path, the memory controller will cancel the request since the speculative read has already been issued. If the request is directed elsewhere or is not a read request, the speculative read request is cancelled.
Abstract: A configuration register used to adjust a clock or request signal with respect to the other. Specifically, a look-up table is provided in the memory controller. The look-up table is filled at bootup such that it contains test information from a master look-up table in the system BIOS, for instance. The look-up table in the memory controller stores current test data correlative to optimal sampling times for the current configuration. Adjustable delay elements or adjustable load elements may be used to change the relative sampling time of the request signal correlative to the values stored in the memory controller look-up table.
Abstract: A differential input buffer circuit includes enabling circuitry that provides a first portion of an operating current to an input buffer. Enabling circuitry provides a second portion of the operating current when data is expected. A process may be used in an input buffer that is adapted to draw an operating current. Such a process comprises the acts of providing a first portion of the operating current to the input buffer and providing a second portion of the operating current to the input buffer if the input buffer is expecting data.
Abstract: A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.
Abstract: A housing for a cable adapter assembly is featured. The housing may comprise a plurality of pieces that may be secured together, each piece forming a portion of the housing. The housing also may comprise a single piece having portions that are secured to each other around the welding cable adapter to form the housing. The single piece housing may be hinged. The housing may house a welding cable connector and the welding cable adapter. A method of converting a welding cable connector from one type of connector to another also is featured.
Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.
Type:
Grant
Filed:
July 16, 2001
Date of Patent:
September 28, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Fernando N. M. Gonzalez, Raymond A. Turi
Abstract: A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.
Abstract: An image data compression technique is provided for compressing an image data stream by selection of one or more compression algorithms from a set of candidate algorithms. Key code representative of the selected algorithm or algorithms is inserted into the compressed data stream to facilitate decompression in accordance with the selected algorithm or algorithms. The image data stream may be broken into a plurality of subregions, and compression algorithms selected for optimal compression of each subregion. Key code identifying the algorithm selected for each subregion is embedded in the compressed data stream to facilitate decompression.
Abstract: A technique for supplying power and data signals to panel-mounted components includes distribution of power and data conductors in a trunk wireway and further distribution to component locations via drop cable assemblies disposed in drop wireways. The drop cable assemblies and trunk cable assemblies may include identical cable. The cables have a plurality of parallel conductors in an insulated jacket. Connectors are mounted on the drop cable assemblies for receiving plug-in component cable assemblies routed to individual components mounted within component panels or bays. The components are thus electrically coupled in parallel with one another and may receive both power and data signals via the drop and trunk cable assemblies coupled to a network. Individual components may be independent installed and removed for servicing with interrupting service to upstream or downstream components in the system.
Type:
Grant
Filed:
November 22, 2002
Date of Patent:
September 21, 2004
Assignee:
Rockwell Automation Technologies, Inc.
Inventors:
Chester Malkowski, Jr., G. Erich Heberlein, Jr., Steven J. Litzau
Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
Type:
Grant
Filed:
August 29, 2002
Date of Patent:
September 21, 2004
Inventors:
Lucien J. Bissey, Kevin G. Duesman, Warren M. Farnworth
Abstract: The present technique provides a variety of processing schemes for decomposing soft tissue and bone images more accurately from low and high-energy images acquired from an imaging system, such as a dual-energy digital radiography system using flat-panel technology. In particular, a modified decomposition process is provided to mitigate noise and to reduce contrast artifacts, such as blooming, while decomposing soft tissue and bone images from low and high-energy images.
Type:
Grant
Filed:
July 9, 2003
Date of Patent:
September 14, 2004
Assignee:
GE Medical Systems Global Technology Company, LLC.
Abstract: A method and device for providing a gate blocking material. Specifically, a method for molding a substrate having known good and bad sites thereon, by blocking the gate area of the bad sites during the molding process. A blocking material or an injection pin are used to interrupt the flow of molding compound through an injection molding system, and thereby prevent molding compound from flowing onto the known bad substrate sites.
Type:
Grant
Filed:
December 24, 2002
Date of Patent:
September 14, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Bret K. Street, Casey L. Prindiville, Cary Baerlocher
Abstract: An image data compression technique includes division of an image data stream into a plurality of subregions and optimal compression of each subregion. The subregions may represent adjacent pixels in a reconstructed image, and may all be of the same length. The length of the subregions may be set to a default, and may be altered based upon image characteristics. The subregions are analyzed for selection of an optimal compression algorithm for each subregion from a set of candidate algorithms. Criteria for selection of the optimal algorithms may include the relative entropy levels of data within the subregions, and the length of compressed data code resulting from application of each of the candidate algorithms.
Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.
Abstract: A technique is described for programming multiple axes or channels of a system, such as an MRI system. Modular component time masks are defined including information for activity on at least one axis and a time boundary for execution of the activity. The modular components may be stored in a library, and assembled to define desired control sequences. Activity may include pulse sequences for coils in the imaging system. The modular components facilitate definition of complex multi-axis control sequences while respecting inherent physical constraints of the system. Time optimized control sequences may be developed from the modular components by reference to beginning and ending times of a series of components, or to anchor time points associated with the components.
Type:
Grant
Filed:
December 29, 2000
Date of Patent:
September 7, 2004
Assignee:
General Electric Company
Inventors:
Graeme Colin McKinnon, Paul Edgar Licato, Qing Tan, Lawrence Edward Ploétz
Abstract: A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.
Type:
Grant
Filed:
April 28, 2003
Date of Patent:
August 24, 2004
Assignee:
Micron Technology, Inc.
Inventors:
Tyler J. Gomm, Aaron M. Schoenfeld, Travis E. Dirkes, Ross E. Dermott
Abstract: A technique is disclosed for enhancing discrete pixel images in accordance with a desired dynamic range, such as the dynamic range of a softcopy display. Adaptive equalization is first performed on the image data to reduce overall differences between high and low intensity values, while maintaining the overall appearance of light and dark regions of the reconstructed image. Adaptive contrast boosting or enhancement is then performed on the equalized values to bring out details visible by virtue of the enhanced local contrast. The contrast enhancement may include non-linear mapping of a mid-frequency boosted image onto the dynamic range of the softcopy display.
Abstract: A technique is provided whereby a solvent spectrum may be displaced from a spectrum of interest using magnetic resonance spectroscopic imaging. The technique utilizes exciting the subject matter with alternating RF pulse sequences. The alternating RF pulse sequences are configured such that the phase of the frequency component corresponding to the solvent is offset each alternation by an amount, typically 180°, which results in full spatial separation of the solvent signal from the signal of interest after processing.
Type:
Grant
Filed:
November 26, 2002
Date of Patent:
August 24, 2004
Assignee:
GE Medical Systems Global Technology Company, LLC
Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.
Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.