Abstract: An integrated circuit in which closer matching or tracking of critical components, both active and passive, is achieved by time domain multiplexing of these critical components. Time domain multiplexing means that each of the components to be matched is alternately and sequentially, electronically switched between selected positions in the circuit. This is accomplished by continuous electronic movement or rotation of the critical components into or out of selected circuit positions to average in the circuit output any inherent errors due to variations resulting from electrical and physical characteristics appearing in the components. This arrangement is particularly useful in compensating for variations induced by the process used to create the components. This time domain multiplexing is especially useful in analog circuits employing complementary metal on silicon (CMOS) transistors, both field effect and bipolar in which component tracking is required for quality operation.

Abstract: A microscope interferometer is described, that scans an object surface through a membrane mask with a multitude of pinholes. Light reflected back through the pinholes interferes with the darkfield image of the mask surface. The mask to object separation can be stabilized by an air flow through the pinholes. Image processing techniques allow to overcome the Abbe diffraction limit for the lateral resolution.

Abstract: The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.

Abstract: An apparatus (2) for transferring wafers between carriers of different densities having a loading station and unloading station; a lift for raising the wafers to be transferred into a wafer handler secured to a support. The wafer handler has two substantially cylindrical arms, cantilevered from the support with each arm provided with slotted rollers for holding and guiding wafers inserted therein. The arms are rotatable in four steps of 90 degrees each to cause the rollers to each take four different positions. A first position is for placing a first set of wafers in selected slots in the rollers, a second for holding the first set of wafers and passing a second set of wafers into a different set of slots interdigitated with the first set of wafers, a third position for holding the first and the second sets of wafers, and a fourth for transferring both sets of wafers into a new carrier. The apparatus can vary the sequence of loading and unloading and is suitable for use in automatic wafer production lines.

Abstract: A method for automatically splitting a layout of a hole pattern into two complementary arrangements for x-ray, electron beam, ion beams, i.e., particle beam masks. The method determines all inside and outside corners of said pattern and determining a stability value for the pattern so the pattern can be divided into stable sections and alternately distributed over two complementary masks.

Abstract: A system for mounting VLSI devices on a substrate is disclosed, offering a high contact density. Each package consists of a semiconductor device having protruding elongated contact pin (2) on its surface and a wiring substrate having a cavity (3) on its surface. The cavities are filed with a conductive material (7) of a low melting point composition and sealed with a thin non-conductive foil (4). During packaging, the contact pins are made to penetrate the foil, and extend into the conductive alloy, thus making electrical contact therewith. To ease the penetration of the foil, the contact pins could be set into oscillating motion by means of an ultrasonic generator.

Abstract: This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires.

Abstract: A molecular restricter for inhibiting or preventing gas molecules from flowing past a point, such as a piece of optical equipment, substantially without inhibiting particles mixed therewith from passing therethrough is described. The molecular restricter has a plurality of elongated cells with each end open to permit the particles to pass through. However the width of the cell must be less than the mean free path .gamma. of the molecules under the conditions the restricter is to be used with. In one embodiment, the length of the cell is at least ten times longer than its width. The cells are arranged adjacent to each other and in parallel orientation. The walls of each cell must also be parallel to permit free transmission of the particles or light therethrough.

Abstract: According to the present invention, an improved chip and leadframe package assembly and method of making the same is provided. The package assembly is comprised of a metal leadframe having a chip bond pedestal centrally located and a plurality of discrete leads surrounding the pedestal. An I/C (integrated circuit) semiconductor chip is mounted on the pedestal, the chip having a plurality of connection or bonding pads disposed around the periphery. An interposer having a layer of dielectric material and discrete metal lines formed thereon is mounted on an apron of the chip bonding pedestal between the location of the chip and the inner discrete leads of the leadframe. Connections are provided between the bonding pads on the chip and the respective lines on the interposer and connections are also provided between the fingers and the respective lines on the leadframe.

Abstract: A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator.

Abstract: A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires.

Abstract: The compressor cascade comprises a plurality of tandem-connected membrane pumps, each of the pumps having a plurality of stroke chambers whose volumes decrease in the direction of the fluid flow through the pumps. Each chamber has several parallel-connected input/output channels for interconnecting the individual membrane pumps and a check valve in each input/output channel for forcing the fluid in a specified direction. By electrostatic attraction forces, the membranes in the pumps are energized synchronously to resonance oscillations of the same frequency and deflection, building up the necessary operating pressure as the fluid is moved from the stroke chamber of one membrane pump into the smaller volume stroke chamber of the next succeeding membrane pump. The movement of the fluid through the membrane pumps of the compressor cascade leads to its compression, and the pressure at the end of the cascade is related to the reduction in volume of each succeeding stroke chamber.

Abstract: A probe for testing integrated circuit wafers is disclosed herein. The probe comprises a ceramic body having an extended voltage contact on the upper most surface, an extended ground contact on the lower most surface, sets of interdigitated internal metallic plates, one set of plates beginning at the voltage contact and extending part way into the body and the other set of plates beginning at the ground contact and extending interdigitally into the body between the other set of plates, but separated therefrom by the material of the body and a needle-like member contacts which connected to one of the needle-like members has a cantilevered tip adapted to contact a semiconductor circuit interconnection pad.

Abstract: Method and an apparatus for determining line centers in a microminiature element such as on a semiconductor wafer or a mask having linewidths and other spacings below the one micron range. The invention uses, two focussed laser beams which are directed across a line on the element, both beams being illuminated successively with a distance therebetween below the classic resolving power. A portion of the incident beam and a portion of the beam reflected from the line is conducted to respective detectors which respectively generate measurement and reference signals. These signals are treated to eliminate high frequency noise components therein. Subsequently, the filtered measurement and reference signals are digitized and synchronously processed to provide two sine shaped curves whose intersection point corresponds to the center of the scanned line.

Abstract: This describes a differential amplifier for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage and comprises two identical voltage networks coupled between differential voltage inputs and to common differential current outputs and a common bias circuit. The described transmission line circuit operates as a transmission line receiver circuit with a high degree of common-mode rejection that will work in a high input signal voltage environment and in which both true and complement outputs can be developed such that their signal responses are additive and their common-mode responses subtractive. The circuit thus converts the input voltage to an input current while isolating the sensing circuit from common-mode input voltages which may be in excess of the breakdown voltage of the individual components of the circuit and the power supplies powering up the sensing circuit.

Abstract: A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors on its top surface is provided with an integrated semiconductor chip having a major surface and contact pads on the major surface in the recess of the carrier, with said contact pads positioned in the region of said slot so that the contact pads can be connected by lead wires passing through said slot, to the conductors on the top side of the carrier. The active surface of the chip containing the contact pads is encapsulated but the back surface of the chip and carrier is left exposed to improve the thermal characteristics of the chip while maintaining a low package profile.

Abstract: The present invention teaches an arrangement for increasing the output impedance of a power amplifier coupled to a capacitively loaded line during the switching of power levels by the amplifier on the line. The arrangement of the invention reduces undesired noise voltage during switching. The present invention achieves this end by using a control circuit composed of a differential amplifier which has one input fed from the junction of an impedance resistor and a transistor that simulate the power stage transistor in the power amplifier being switched. This control circuit provides control voltage outputs to power control transistors which are connected to and control the speed of the power stage transistors used to change and discharge the capcitively loaded line.

Abstract: A plastic encapsulated semiconductor package in which the connecting lead frame members are deposited over the surface of the device together with a covering ground plane so as to provide enhanced electrical and thermal coupling of the members and the device and so reduce the signal to noise ratio by a factor or greater than three over that available in other similar plastic encapsulated packages while simultaneously improving the transfer of heat out of the package.In particular, a lead frame having a plurality of conductors is attached to a major active surface of a semiconductor chip via a ground plane which, in the preferred embodiment, is a multilayered structure containing an insulated integral, uniform ground plane positioned between the lead frame and the chip and adhesively and insulatively joined to both of them. Wires connect terminals on the major active surface of the semiconductor chip to the ground plane and to selective lead frame conductors.

Abstract: The present invention is directed toward an improved etching solution which is a five component system and does not use ethylene-diamine. This etch will preferentially etch lightly doped, single crystalline silicon at an etch rate of 0.6 microns per minute .+-.0.05 microns per minute and will effectively stop at a selectively doped level in the silicon body being etched because the etch rate of this selectively doped level drops from 0.6 microns per minute to between 0.001 microns per minute and 0.0006 microns per minute. The etch is comprised of ethanol-amine, piperidine, water, pyrocatechol and 30% hydrogen peroxide. The solution preferably consists of 28 mls. ethanol-amine, 2 mls. piperidine, 5.5 mls. water, 5.5 grams pyrocatechol and 0.25 mls. hydrogen peroxide. If desired a trace of a long chain surfactant can be added to the solution.

Abstract: In an encapsulated semiconductor module in which a semiconductor chip, having a major surface with terminals thereon, is deposed within the encapsulating material, a plurality of self-supporting, unitary, discrete, and continuous lead frame conductors formed of metal sheet stock are positioned at various locations around the chip and cantilevered out of the encapsulating material, so that discrete wires can be used to connect respective ones of said conductors to respective ones of said terminals. In the present invention excessively long bonding wires are avoided by connecting a selected one of said lead frame conductors to a parallel conductor by a jumper wire and connecting the parallel conductor to the desired terminal with a short wire.