Abstract: A hybrid connector system comprising a special jack, a standard coaxial plug effective to make contact with the jack in one mode when inserted therein, and a wire pair plug operable to engage the special jack in another mode when plugged thereinto, the wire pair plug element being adaptable to, or configured especially for, use with shielded twisted pair cables, unshielded twisted pair cables, or ordinary telephone lines. The jack or socket member has first second and third concentric contact members, two of which are arranged to engage respectively, the central and shell contacts of a coaxial cable plug. The third of the contact elements of the socket member is interposed between the first and second contact elements, and the three contact elements are positioned to engage corresponding contact elements of the special plug which, when inserted into the socket completes connection to first and second ones of a wire pair and, optionally, a shield of such wire pair.

Abstract: In a CRT display system, its screen is divided into a least two partitions or viewports for displaying different data groups, and characters in one of the groups can be vertically scrolled bit by bit in one of the partitions. The partition to be scrolled is defined by line attributes assigned to successive rows of the screen. When a raster scan passes the scrolling partition, a line count output of a (scan) line counter is modified by adding a content of a smooth scroll offset register to the line count. The modified line count is used together with a character code as an address for a character generator. By gradually changing the content of the offset register, the characters are vertically shifted smoothly in the partition.

Abstract: A regulated voltage electrical power system has a driving section and a driven section. The driving section includes a power transformer primary structure and a ripple current carrying, driving winding of a filter system for the smoothed outputs circuits of the power system, each of which includes a single turn, driven filter winding magnetically coupled to the driving winding by a multi-path core structure. Each driven filter winding links that part of the multi-path structure which corresponds in cross-sectional area to the relative ripple voltage imposed by the power transformer on it. The power transformer secondaries for the outputs of the power system are also of a single turn each, differing output voltages being achieved by provision of differing number of primary winding turns associated with the various outputs. Planar diodes and core gap-filling ferrite inserts are provided in the secondary winding structures.

Abstract: A display terminal of the type which is dependent on a remote processor for its operation and for its main data storage, comprising an interactive language interpreter (24) (e.g. for BASIC), terminal processor, local storage, display and a switch for switching between a session (90) associated with the remote processor and a session (91) dedicated to servicing the interactive language interpreter (24). During an interactive language session screens of data associated with the host session may be displayed and then saved which enables host data to be processed using user programs in the interactive language.

Abstract: A transformer structure includes two planar primary windings in a single plane with one primary winding on each leg of a core. The primary windings are connected in series or in parallel. The secondary structure includes a planar conductor structure about the core. A conductor passes through the core and makes electrical connection to the planar conductor through diode rectifiers. An anti-phase embodiment has dual primary circuits and dual cores with a combined secondary structure. Both plate-form and circuit card form embodiments are disclosed.

Abstract: A regulator includes a switching transformer (TR) whose primary winding is divided into two halves through which current flows alternatingly via one respective switching transistor (Q1, Q2). The pulses on the secondary side of the transformer are rectified to attain the output voltage. The output voltage is controlled by pulse width modulated driver pulses for the two switching transistors. A protective circuit (12) with immediate effect terminates the currently applied driver pulse when the current flowing through the conductive switching transistor reaches a critical current value. A protective circuit (14) with delay effect prevents the generation of further driver pulses upon a further increased overload, this prevention being limited with respect to time. The protective system directly is controlled by the primary current of the power regulator.

Abstract: The present invention deals with rotating an n.times.n block of bits through an angle of +90 degrees or -90 degrees by a method including the steps of: storing the data in a matrix; separating the matrix into groups of bits of rotatable size; transposing first preselected bit positions with second preselected bit positions in each group; and exchanging a first one or more rows of bits in the group with a second one or more rows of bits in the group.

Abstract: A method for identifying a bounded area of a graphic display. The method uses the division of the display screen into nine areas then the central square is the correlation window. This window can be small, two or three pel width, or large if the application is seeking to identify a larger area. The point indicated by the operator is in the center of the correlation window. An object (bounded area) which intersects this square will register a bit. It can be seen that a bounded area will intersect the correlation window if either: (a) any part of the boundary actually passes through the window, or (b) any arbitrary point within the window is inside the area.

Abstract: A graphics display apparatus employs a general purpose or main microprocessor providing general control of the apparatus including receiving high-level graphic orders defining a desired graphic image from a host processor and dedicated graphics microprocessor connected to receive low-level graphic orders from the general microprocessor along a pipeline constituted by a shared buffer store. Pipeline control logic controls the pipeline by blocking the graphics processor which generally operates more quickly than the general processor until the latter has completed computation of all the low-level orders associated with a particular high-level order. The front-of-screen performance can be further improved by backing up the pipeline to repeat certain low-level orders rather than by obtaining these repeated orders by recomputation. Graphics hardware controlled by the graphics processor loads appropriate bit patterns into an all points addressable refresh buffer for subsequent display on a cathode ray tube monitor.

Abstract: In a computer terminal system, a communications buffer is provided in a remote device to receive and transmit data and control information from and to the remote controller via the transmission link connecting the two. The controller owns the buffer and places data at any point in the buffer and places data at any point in the buffer and tells the device to process it. The controller may write the data to another point in the buffer allowing full overlap.The controller can read data from the buffer or write data to the buffer while the device is processing. The controller is able to manage the use of the device buffer in accordance with the specific environment in which the controller is operating.

Abstract: A d.c. to d.c. converter system converts a d.c. signal into a pulsating a.c. signal, which is applied to the primary of a power transformer. A transformer in which the primary and secondary windings are planar is employed to generate the output pulse signal. The planar transformer design provides the inductance required to filter the output signal and reduce the ripple therein, while simultaneously providing tight coupling between the primary and secondary windings. A single turn secondary winding is provided to reduce the number of turns in the transformer and thereby reduce the associated power loss.

Abstract: In a digital data processing system having a resource which is shared between a plurality of users, an arbitration system comprises a plurality of resource requestors (14 to 16) each associated with a respective user, and a resource grantor (10) to which the requestors are connected in parallel via a set of common lines (11 to 13). Each resource requestor is adapted to apply a request signal on a predetermined first one (11) of the lines when the associated user requests the resource, and the resource grantor is responsive to the presence of a request signal on the first line to subsequently apply a grant signal on a predetermined second one (12) of the lines to grant the resource. Each resource requestor requesting the resource is responsive to the grant signal to apply an accept signal on a predetermined third one (13) of the lines after a delay which is different for each resource requestor and which determines the priority of the user associated with the resource requestor.

Abstract: A CPU initializes pluggable adapters with built-in identity and conditional ROS and complies a Hardware First Level Interrupt Handler (HFLIH) table of identity against status register address and a Software First Level Interrupt Handler (HFLIH) table of identity against on-board system function. It stores the tables with a control module in enabled memory on the keyboard adapter. Conditional ROS is enabled on a given adapter receiving a broadcast of its own identity. Adapter interrupts are ORed. HFLIH is stepped through by the control module to access adapter status sequentially, servicing each adapter in turn from its ROS, using its broadcast identity. The enabled adapter appears as a single entity to the central processor and occupies a single window in the address space which is common to all of the adapters but used by only one at a time. System functions are accessed via HFLIH.

Abstract: A linear output multiplier has two pairs of differentially connected multiplying transistors (T13, T14 and T15 T16). One value Vx to be multiplied is supplied to the differential inputs of differential amplifier 1 and converted to corresponding differential currents I1 and I2. These currents are supplied to semiconductor junctions which generate logarithmically distorted voltages representing the one value Vx which are applied to the control electrodes of the multiplying transistors. The second value Vy to be multiplied is supplied to the differential inputs of differential amplifier 2 and converted to corresponding differential currents I3 and I4. The outputs from amplifier 2 are connected respectively to the tail connections of the two differential pairs of multiplier transistors. The outputs of the multiplying transistors are cross-coupled to provide four quadrant multiplying functions.

Abstract: An interrupt interface circuit for connection to a shared interrupt request line. An internally generated interrupt impresses an interrupt request line and also locks out any further interrupt requests until the interrupt request is analyzed to be of a minimum duration, in which case the lock out is latched. An interrupt request on the shared interrupt request line is also analyzed for minimum duration before it causes a lock out to be latched. A latched lock out is removed by a signal generated by the interrupt handler.

Abstract: A terminal controller system is described wherein several feature cards are plugged into slots on a board, and I/O signal cables are connected between cards and/or remote multiplexors or terminals. A special purpose card identification (ID) bus is driven by the feature cards and received by an ID adapter. The ID adapter has one select line running to each of the slots on the board. The ID adapter enables the select lines one at a time, whereby the selected feature cards drive their IDs onto the ID bus. A processor records the slot population by ID and also can analyze the IDs to determine if a valid configuration exists. The processor then performs a wrap test on each of its ports. This test alters the ID which it wraps and by comparison with the IDs recorded originally, this enables the processor to logically establish the physical link to particular cards connected to the ports.

Abstract: An FET full bridge regulator has a driving transformer for the gates of the power FETs of the regulator, and a driving circuit for the primary of the driving transformer, the driving circuit including a full bridge formed by first and second sets of driving FETs, each set formed by a complementary pair of FETs and being connected across the transformer, primary, one FET of each set being driven ON to together form a series of conducting paths across the primary of the transformer in the absense of driving signals.The voltage supply for the driving FETS in the driving circuits of the primary of the driving transformer includes a resistance across which there is developed a voltage proportional to the current drawn by the driving transformer primary in each half cycle of its operation for reducing imbalance between the half cycles.

Abstract: The specification describes a method of storing alphanumeric characters in a graphics display terminal comprising a raster-scan display device and a refresh buffer including a plurality of bit planes each having a respective bit storage location corresponding to each addressable pel position on the screen of the display device. In the method, a first bit plane stores high resolution luminance data defining alphanumeric characters each as a selection of "on" bits within a respective n.times.m array where n is the width of the character box in the scan line direction, and at least one further bit plane stores low resolution color data for the characters. The attribute plane comprises a respective n-bit set of storage locations which corresponds to each n-bit wide by one pel deep portion of a character box in the luminance plane and defines at least the color and/or intensity of the foreground and background of the character for the width of the character box in respect of a single scan line.

Abstract: An electronic funds transfer system (EFT) is described in which retail terminals located in stores are connected through a public switched telecommunication system to card issuing agencies data processing centers. Users of the system are issued with intelligent secure bank cards, which include a microprocessor, ROS and RAM stores. The POS includes a personal key (KP) and an account number (PAN) stored on the card when the issuer issues it to the user. Users also have a personal identity number (PIN) which is stored or remembered separately.A transaction is initiated at a retail terminal when a card is inserted in an EFT module connected to the terminal. A request message including the PAN and a session key (KS) is transmitted to the issuers data processing center. The issuer generates an authentication parameter (TAP) based upon its stored version of KP and PIN and a time variant parameter received from the terminal.