Abstract: An electronic funds transfer system (EFT) is described in which retail terminals located in stores are connected through a public switched telecommunication system to card issuing agencies data processing centers. Users of the system are issued with intelligent secure bank cards, which include a microprocessor, ROS and RAM stores. The ROS includes a personal key (KP) and an account number (PAN) stored on the card when the issuer issues it to the user. Users also have a personal identity numbe (PIN) which is stored or remembered separately.A transaction is initiated at a retail terminal when a card is inserted in an EPT module connected to the terminal. A request message including the PAN and a session key (KS) is transmitted to the issuers data processing center. The issuer generates an authentication parameter (TAP) based upon its stored version of KP and PIN and a time variant parameter received from the terminal.

Abstract: A graphics display apparatus includes a raster-scanned CRT refreshed from a bit-for-pel refresh buffer loaded with bit patterns by a microprocessor corresponding to a desired image. To display shaded areas, additional control logic draws an outline of the area in an auxiliary memory, preferably using Bresenham's Algorithm, according to specified rules. Edge filling logic consisting of EXCLUSIVE-OR gates is used to draw the filled area in the refresh buffer as the outline is read from the auxiliary memory into the refresh buffer. This hardware assistance by the control logic and edge fill logic to the microprocessor enables complex areas to be drawn and filled without unduly degrading the performance of the microprocessor.

Abstract: A technique for reducing RSA (Rivest, Shamir and Adleman algorithm) cryptovariable key from 1200 bits (400-bit public key, 400-bit secret key and 400-bit modulus) to 106 bits makes feasible the storage of the RSA algorithm parameters on current magnetic stripe cards used by the banking and finance industry. Of the 106 bits required, only 56 bits must be kept secret; the remaining 50 bits are nonsecret. These 106 bits are used to derive two 200-bit primes P and Q from which is computed the modulus N=PQ and two 400-bit keys PK (public key) and SK (secret key). In effect, a savings in storage is achieved at the expense of performing a precomputation to derive the modulus and keys each time the system is utilized for encryption/decryption. The 56-bit value plus the additional 50 bits of nonsecret data can be used to generate the RSA cryptovariables in systems where the RSA algorithm has been implemented.

Abstract: A method and apparatus for automatically changing the display in overlapping rectangular viewport areas of a display screen of a digital display apparatus and in which each viewport area is assigned a different priority level. The method includes the steps of (a) storing in a random access store indications of the position and size of each viewport area, together with an indication of the priority level of the viewport area and (b) constructing a first matrix of (2n+1).sup.2 elements, where n is equal to the number of viewport areas, by assigning a vertical component to each vertical coordinate of each viewport area and a horizontal component to each horizontal coordinate of each viewport area, and for each element so formed storing an indication of the highest priority level of the viewports falling within the boundary formed by the coordinates defining the element.

Abstract: The described embodiment provides listing control on a cathode ray tube (CRT) display for simultaneously drawing horizontal and vertical grid lines within a square box displayed on the CRT screen by moving a cursor to the intersection point of these grid lines and by pressing an ENTER key.The embodiment uses a current position counter, a starting point counter and ending point counter to selectively set flag bits for horizontal and vertical grid lines stored in a logical page buffer so that the horizontal and vertical grid lines passing through the intersection point can be simultaneously displayed on the CRT screen. The embodiment uses the counters to define two end points on a diagonal line of the square box and to define the intersection point within the square box, whereby the flag bits are selectively set in accordance with the contents of these counters.

Abstract: In an interactive graphics display system in which pels in a frame buffer are mapped to the display screen of a raster display device, a method of automatically highlighting and de-highlighting graphic segments as a cursor is moved across the display screen comprises sampling a locator device at successive points in time to generate a screen cursor at corresponding positions on the screen, examining pels in the frame buffer along a line which extends from the pel corresponding to the previous cursor position to the pel corresponding to the current cursor position to determine whether a pel is "on" along the line, automatically performing a correlate operation in respect of the "on" pel (if any) to identify the graphic segment associated with that pel, and highlighting the segment so identified, any highlighted segment being de-highlighted prior to highlighting a different segment.

Abstract: The invention provides a display apparatus for producing a color image in which the color of each picture element is defined by the intensities of component red, blue and green primaries and is coded as a binary number having r bits defining 2.sup.r intensity levels for red, g bits defining 2.sup.g intensity levels for green, and b bits defining 2.sup.b intensity levels for blue, where g.ltoreq.7, (g-r)=1 or 2, and (g-b)=2. In a particularly advantageous embodiment of the invention the image has a resolution of substantially 4 pels per mm or greater, and g.ltoreq.4.The invention also includes a method of coding a color image as defined above.

Abstract: A dot pattern source image stored in a pattern memory is moved to a specified location in the pattern memory in an angle of n.times.90.degree. (n=0, 1, 2, or 3) with respect to the source image. First, area definition is made for a rectangular source area including the source image to be moved and a rectangular destination area where the source area is to be positioned after the move processing. Then, the positions of four sides of the source and destination areas are compared to determine, for each side, whether there is a processable side region which is included in the destination area but not included in the source area. When such a processable side region is found along one side, the image data in a corresponding region of the source area is moved to the processable side region with a specified angle relative to the source image data.

Abstract: A power supply circuit for producing at least one output which is essentially free from current ripple is disclosed. A chopped DC voltage source is applied to a transformer having a primary coil and at least two secondary coils. The secondary coils provide input voltages to output stages which each include a rectifier diode, a freewheeling diode and an LC filter. The inductors in the LC filter of adjacent output stages are magnetically coupled together. The characteristics of these inductors are selected such that the current ripple through the inductors in all the output stages, other than the first output stage, is essentially zero. Multiple inductors can also be employed in the first output stage with each one being magnetically coupled to the inductor in a different succeeding output stage.These multiple inductors in the first output stage can be combined in series or in parallel.

Abstract: A method of determining the coincidence of a subject area and a clip area in a graphic display system, comprising creating three parts list, one for parts of the subject area that are outside the clip area, a second for parts of the clip area that are inside the subject area and a third for overlapping lines. The parts of the subject area which lie outside the clip area are defined by examining the parts lists. The output can then be used to control a pen plotter, in which different colors are used so that underlying areas do not have to be linked over with overlay colors.

Abstract: Primary and secondary data save areas are established in a volatile memory (CMOS) which is backed up with a battery. The same predetermined data are stored in the primary and secondary data areas together with check sum. At a power on time, the data of the primary area are added together and the data of the secondary area are added together. When both of results of the addition are equal to the check sum, no error is detected. When only one of results of addition is different from the check sum, an intermittent error is detected. When both of results of addition are different from the check sum, battery exhausted condition is detected. If the intermittent error is detected, data of one area whose result of addition is equal to the check sum are copied to other area whose result addition is different from the check sum.

Abstract: A display system is disclosed comprising a processor, a plasma panel subassembly including generally orthogonally related arrays of conductors and drive circuits for the same, and a read-write memory for storing the image data provided by the processor and delivering drive information to the panel subassembly. Control logic provides arbitration for time sharing the operation of the memory between communication with the processor and with the panel subassembly, storage of modified data tags means associated with the memory operation, and means under the control of the modified data tag means to control update erase and write operations of the panel subassembly on an as-needed individual pel line basis.

Abstract: A test system of this invention is capable of distinguishing interface circuit trouble from keyboard trouble. For diagnosis, an inhibit signal is generated to supply a test clock signal to an output shift register and an input shift register of the interface circuit instead of a clock signal generated from the keyboard, and test data are loaded into the output shift register. If the test data are transferred from the output shift register to the input shift register correctly, it is detected that the interface circuit does not have trouble.

Abstract: A multi-window display station having main frame (host) interactive and local personal computer display data buffers is provided. The outputs of the two data buffers are merged, using a row or swath buffer, according to default or escape codes stored in one of the data buffers and the combined output drives a plasma panel display. Registers for modified data tags and for presence/absence of escape codes speed the panel update process. Means are included to provide alpha-numeric and graphic windows together on the panel screen.

Abstract: An interactive raster-scanned display device has a microprocessor (1) and random access memory (3) which operate to issue instructions to a drawing engine (7) to cause it to load and erase image pel representation in an image buffer (9) in order to control display of images on, or removal of images from a display screen (8) in a conventional manner. A cursor control device (10) enables a user to interact by means of a cursor symbol with images on the screen. In order to reduce the demands imposed on the drawing engine during transformation of images over the screen, the system is configured so that transformation operations are performed using alternative images substituted for the full images. Each alternative image contains considerably less detail to be drawn and erased than the full image it replaces and therefore the operation is more likely to be performed at the rate desired by the user.

Abstract: A graphics display apparatus employing a raster scanned cathode ray tube uses a refresh buffer constituted by a coded alphanumeric buffer and an associated character generator for displaying alphanumeric characters and other symbols and an all-points-addressable buffer for displaying graphics. Serialized data from the two buffers are mixed in a mixer under control of at least one control bit (attribute) stored in the coded buffer to provide a composite pel-representing bit stream supplied to the cathode ray tube.