Abstract: A deflection distortion correcting circuit for CRT display with interlaced scanning is disclosed, which correct concurrently both linearity of vertical deflection and pairing of horizontal interlaced scanning lines which is caused by variation in anode voltage. This can be achieved simply and easily by combining an adder with a conventional cubic curve linearity correction circuit to introduce a pairing correcting component related to the variation in anode voltage into the cubic curve linearity correction.

Abstract: A cathode ray tube display apparatus is provided comprising a regenerating buffer memory, a row address table and a pointer. The regenerating buffer memory has a greater storage capacity than the display capacity of the CRT screen and stores character information. The row address table has a capacity storing more addresses indicating the rows in the regenerating buffer memory than the number of rows on the CRT screen. The pointer designates an address of the table for determining the stored position of the regenerating memory to be first accessed by the table. This cathode ray tube display apparatus is capable of scrolling and paging easily and quickly without changing the content of the regenerating buffer memory and the row address table.

Abstract: A convergence unit for an in-line color cathode ray tube consists of two E-shaped cores, preferably formed of strip-shaped soft-magnetic material. Each E-core has two relatively long limbs extending from a central relatively short pole piece to end relatively short pole pieces windings extend around the limbs which are substantially parallel to a tangent to the neck of the CRT so that the magnetic fields due to individual turns reinforce the magnetic fields between the pole pieces.Preferably each E-core has each of its two windings extending over both limbs, one being reverse wound, so that the mutual inductance between the two windings is zero.

Abstract: A digital data display system in which the display device includes a plurality of random access stores into which character cell definitions are loaded from a remote central processing unit. A character cell may be a 9.times.16 picture element matrix and each is defined in the CPU according to the requirements of a display request received from a users application program. The system control services include a graphics manager and graphics routines which construct a character buffer and character cell definition table according to the picture to be displayed. A character cell definition that is required more than once in a picture is only included once in the definition table, the character buffer having the required number of pointers to the one definition. When the character buffer and character definition table have been constructed, they are transmitted to the display device using a data communication system. The system can be used for color or monochrome displays.

Abstract: Non-linearities of an electron beam in a cathode ray tube are corrected in accordance with the position of the beam by circuitry which completes the correction from stored digital values. In response to positional signals X and Y, correction waveforms are generated in analog circuits 8H, 8V and 10. The waveforms are scaled by circuits 11 in accordance with the stored digital values and are summed in circuits 9R to 9L and applied to the windings of the cathode ray tube. Preferably the invention is applied to the correction of misconvergence in a shadow mask color tube.

Abstract: A convergence unit for an in-line color cathode ray tube consists of four E-cores located around the neck of the CRT. Each E-core, preferably consisting of strip-shaped soft-magnetic material such as mumetal or permalloy, carries two coils connected so that the net magnetic field at the central beam is zero. The E-cores are arranged in paris with the resultant fields at the nearer electron beam due to each individual E-core being substantially orthogonal to one another.

Abstract: The dimensions and light output of a beam in a shadow mask cathode-ray tube are determined by means of an optical system 7 focussed on a phosphor dot to pick up and record the light generated by a ray 4 passing through a single aperture 6 in the shadow mask 2. The cathode-ray beam 1 is moved so that the whole cross-section of the beam passes the aperture 4. The detected light outputs are plotted to provide an accurate representation of the whole beam.

Abstract: Circuit for detecting a fault current in an installation where the load (RL) varies. Total current (IS) is converted into a voltage (VS). During an initialization cycle, means such as counter (9), digital-to-analog converter (10), comparator (5), resistors (R1, R2) generate a voltage (VS) equal to VS at the end of the initialization cycle, and a threshold voltage VS=kVS. During operation, voltage VS is compared with threshold VD in order to provide a fault detection indication which is transmitted to the protection circuit by a logic circuit, that is, AND gate (17) and OR gate (19). During the initialization cycle, protection is obtained by comparing VS with a reference voltage in a comparator (7). This device is used to protect machines having an expandable configuration.

Abstract: Aberrations of an electron beam are corrected as the beam is scanned across the screen of a cathode ray tube by deriving correction signals from stored digital values by means of the calculus of finite differences. The digital values, which are the initial differences of polynomial correction functions, are held in store 10 and summed in adder 20, the results being converted by digital-to-analog converter 50 to analog signals and supplied to the cathode ray tube. Provision is made for the reduction of error in the calculations by shifting higher order differences relative to lower order differences before addition. The circuitry may be implemented on a single chip. Preferably, the invention is applied to the correction of misconvergence in a shadow mask tube.

Abstract: Multibeam cathode ray tube apparatus incorporates control circuits for maintaining the relative intensity of the beams over a range of settings of the brightness control. As applied to a three beam color tube, at least two, and preferably all three, of the electron guns have each a control circuit located between the control grid (V.sub.gl) and a variable voltage source (V) which constitutes the brightness control of the display. A potentiometer (R.sub.1) allows the voltage (V) to be variably attenuated and a second potentiometer (R.sub.2) acting in conjunction with a current source (I) allows the attenuated voltage to have a variable voltage added thereto. The potentiometers (R.sub.1 and R.sub.2) for each electron gun are adjusted to bring the brightness versus control voltage characteristic for each gun into coincidence. The current source (I) may be constituted by a fixed resistor and a fixed voltage. The invention is also applicable to multibeam monochrome tubes.

Abstract: Convergence of the beams of an in-line gun shadow mask cathode-ray tube is provided by windings on a common core and generating pairs of quadruple and six-pole magnetic fields, respectively. The core is provided with non-magnetic ribs each having a projection for the purpose of locating the windings.

Abstract: A raster display apparatus capable of displaying graphic pictures includes a processor 13 for loading character codes (pointers) in a character buffer 12. The pointers address a character/cell generator 22 to derive the bit patterns necessary to refresh the display 1 under control of refresh logic 19. As the picture becomes increasingly complex, requiring more and more different character cells, the character/cell generator 22 fills. Space is created by combining two or more adjacent cells into a single low-resolution-displayed cell: an op code associated with each character code (pointer) determines whether the cell is to be displayed at full or reduced resolution and causes the refresh logic to clock bit patterns associated with low resolution cells at a slower rate. Optionally, the processor 13 changes low resolution parts of the picture to high resolution when an operator interacts with the low resolution part using a light pen 30.

Abstract: A line scan circuit for a cathode ray tube display includes a phase detector (3), integrator (4), voltage controlled oscillator (5) and line output stage (6). The integrator, voltage controlled oscillator and line output stage are conventional, but the phase detector is novel. The phase detector compares the phase difference for both the leading and trailing edges of the horizontal synchronization pulses and the line flyback pulses. This forces the line flyback pulses to be centered with respect to the synchronization pulses resulting in improved centering and linearity of the displayed picture.

Abstract: Disclosed is a display system having one or more display terminals, each of which includes a base unit which acts as a display and supports a keyboard for operation as a keyboard/display terminal, the terminal in turn interfacing with a plurality of features connected thereto. The features can be quite independent of the display, such as a card reader, or can be an operationally integral part thereof, such as extended capacity buffer operating jointly with the main buffer of the display, or can be interactive with the display, such as a selector pen or program function keyboard. The base unit and the features receive transmissions from a controller via a feature bus-out in the base unit and transmit to the controller via a feature bus-in in the base unit. The base unit also provides priority control in permitting features to respond to a controller poll.

Abstract: A display system having a scanned CRT provides a full screen layout of alphanumeric characters and at least one additional screen layout, e.g. a split screen layout.A refresh buffer stores data to be displayed in a first sequence of addresses so that when this data is read out by address generator in the first sequence a full screen layout results. A read only translation store may be selectively addressed by the first sequence of addresses to provide a modified sequence of translated addresses. When the refresh buffer is addressed by the sequence of translated addresses, a split screen layout of the data results. A selector is operable to address the refresh buffer with either the first sequence of addresses or the sequence of translated addresses.Logic inhibits character display in a blank area between the two halves of the split screen. Attribute decode logic enables different attributes to control screen halves during split screen operation.