Abstract: The present invention discloses a method including providing a substrate; forming a dielectric material over the substrate; forming an opening in the dielectric material; treating a surface of the dielectric material; forming a conductor in the opening; and planarizing the conductor. The present invention further discloses a structure including a substrate; a dielectric material located over the substrate, the dielectric material having a low dielectric constant; an opening located in the dielectric material; a treated layer located over a sidewall of the opening; and a conductor located in the opening and over the treated layer.

Abstract: The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal. The present invention also discloses a structure including: a substrate; a first interlayer dielectric located over the substrate; a first adhesion promoter layer located over the first interlayer dielectric; an etch stop layer located over the first adhesion promoter layer; a second adhesion promoter layer located over the etch stop layer; and a second interlayer dielectric located over the second adhesion promoter layer.

Abstract: The present invention discloses an apparatus having a platen; a polishing pad disposed over the platen; a slurry dispenser disposed over the polishing pad; a cathode connected electrically to the polishing pad; a wafer carrier disposed over the polishing pad; an anode connected electrically to the wafer carrier; and a power supply connected to the anode and the cathode. The present invention further discloses a method to remove a surface layer from a wafer using a polishing pad, a slurry, and an electrical current.

Abstract: The present invention describes an apparatus that includes a polish pad, the polish pad including a first through-opening; a vertical distribution layer located below the polish pad, the vertical distribution layer connected to the through-opening; a lateral distribution layer located below the vertical distribution layer, the lateral distribution layer connected to the vertical distribution layer; and a slurry dispense located over a front-side of the polish pad, the slurry dispense to provide a slurry to be transported through the polish pad to the lateral distribution layer. The present invention further describes a method including dispensing a slurry at a front-side of a polish pad; flowing the slurry to a location below the polish pad; flowing the slurry upwards and outwards, towards edges of the polish pad; and distributing the slurry to an upper surface of the polish pad.

Abstract: The present invention describes a method including providing a component, the component having a bond pad; forming a passivation layer over the component; forming a via in the passivation layer to uncover the bond pad; and forming an under bump metallurgy (UBM) over the passivation layer, in the via, and over the bond pad, in which the UBM includes an alloy of Aluminum and Magnesium. The present invention also describes an under bump metallurgy (UBM) that includes a lower layer, the lower layer including an alloy of Aluminum and Magnesium; and an upper layer located over the lower layer.

Abstract: The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layer, the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.

Abstract: The present invention includes a mechanical joint between a die and a substrate that is reflowed by microwave energy and a method of forming such a mechanical joint by printing a solder over a substrate, placing the solder in contact with a bump over a die, reflowing the solder with microwave energy, and forming a mechanical joint from the solder and the bump.

Abstract: The present invention discloses a mask having a substrate; a lower multilayer mirror disposed over the substrate, the lower multilayer mirror having a first region and a second region; a buffer layer disposed over the second region of the lower multilayer mirror; and an upper multilayer mirror disposed over the buffer layer. The present invention further discloses a method of forming such a mask.

Abstract: The present invention claims a binary mask printing a product feature which includes a narrow space; and a phase-shifting mask having an assist feature that fits within the narrow space when both masks are properly aligned in exposing a wafer.

Abstract: The present invention discloses a microelectromechanical system mask with an array of reflectors, each reflector having two mirrors separated from each other by an adjustable gap.

Abstract: The present invention discloses an EUV mask having an improved absorber layer with a certain thickness that is formed from a metal and a nonmetal in which the ratio of the metal to the nonmetal changes through the thickness of the improved absorber layer and a method of forming such an EUV mask.

Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.

Abstract: The present invention describes an apparatus comprising an optical array generating a distribution of partial coherence of light energy and an aperture to select a subset of said distribution of partial coherence.

Abstract: The present invention includes a method of providing a first substrate; forming an insulator over the first substrate; forming an opening in the insulator; forming a conductor over the insulator and in the opening; removing the conductor over the insulator with a first chemical-mechanical polish process to leave the conductor in the opening; and reducing thickness of the insulator with a second chemical-mechanical process to permit the conductor in the opening to protrude. The present invention further includes a structure having such a conductor that protrudes.

Abstract: The present invention discloses a method of increasing the contrast of an EUV mask at inspection by forming a multilayer mirror over a substrate; forming an absorber layer over the multilayer mirror; forming a top layer over the absorber layer; patterning the mask into a first region and a second region; and removing the top layer and the absorber layer in the first region.

Abstract: The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.

Abstract: The present invention comprises a tool for and a method of inspecting a mask used in photolithography to determine errors in phase, amplitude, and pattern edges. An embodiment of the tool comprises a laser source, a polarizing beam splitter, a first shutter, a mask, a second shutter, a quarter wave retarder, a single-mode optical fiber, and a CCD detector array. An embodiment of the method comprises four independent measurements of light intensity, comprising: a pattern of a mask, a diffraction pattern of a reference pinhole, an interference pattern of the mask and the reference pinhole, and an interference pattern of the mask and the reference pinhole with a known phase difference. Calculations are performed to determine phase and amplitude information as a function of location on the mask. The phase and amplitude information is then compared with a design layout of the mask to determine pattern edge information and identify possible defects in the mask.

Abstract: The present invention describes a method of forming a mask comprising: providing a substrate, the substrate having a first thickness; forming a balancing layer over the substrate, the balancing layer having a second thickness; forming an absorber layer over the balancing layer, the absorber layer having a first region separated from a second region by a third region; removing the absorber layer in the first region and the second region; removing the balancing layer in the second region; and reducing the substrate in the second region to a third thickness. The present invention also describes a mask comprising: an absorber layers the absorber layer having a first opening and a second opening, the first opening uncovering a balancing layer disposed over a substrate having a first thickness, and the second opening uncovering the substrate having a second thickness.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.