Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.

Abstract: A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH.sub.3). By the inclusion of silane (SiH.sub.4), tantalum silicon nitride (TaSiN) (64) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400.degree. C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties.

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Abstract: A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.

Abstract: A substrate (17) is probed after the planarity between a chuck (16) (or the substrate (17)) and a surface of the probing system (20), such as the bottom surface of the interface (28) or test head (22), has been checked. In one method, a measuring tool (30) having a sensor (36) is placed on a chuck (16) of the probing system (20). A distance between a sensor (36) and a surface within the probing system (20) is measured using the sensor (36). The surface is relatively flat. The sensor (36) remains spaced apart from the surface during the measuring. The measuring tool (30) is removed from the chuck (16). The substrate (17) is placed over the chuck (16) after removing the measuring tool (30) and is probed using the probing system (20). Alternatively, more than one sensor (36) can be used. Further, the sensor(s) (66, 76) could be integrated into the chuck (16), interface (28), or test head (22), thereby not requiring a separate measuring tool (30). Additionally, the method can be automated.

Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).

Abstract: A process for selectively plasma etching polycrystalline silicon or polysilicon in preference to silicon dioxide which minimizes the detrimental effect of carbon. It has been discovered that carbon from the plasma etch chemicals or from photoresist present interferes disadvantageously with the selective plasma etch of polysilicon as opposed to silicon dioxide. By heat treating and deep ultraviolet light treating the photoresist prior to the plasma etch step and by using non-carbon etch chemicals, this detrimental carbon effect can be reduced.

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Abstract: Deuterated compounds are used to form passivation (20) and other insulating layers to reduce the hydrogen content within those films. Semiconductor source gases, nitride source gases, and dopant gases can be obtained in deuterated form. Process steps for forming and etching are substantially the same as those used to form and etch conventional insulating layer. A sintering step can be performed using deuterated gas or omitted altogether.

Abstract: Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

Abstract: A method for forming a semiconductor device in a semiconductor device manufacturing apparatus (20) having a sensor (30) activated extensible shuttle (28). In a fabrication environment shuttle (28) is housed within semiconductor device manufacturing apparatus (20), where an outer door (32) is closed flush with an outer wall of the apparatus (20). As a substrate carrier (38) is moved near the apparatus (20), sensor (30) activates opening of outer door (32) and extension of shuttle (28) out of the apparatus (20) into the fabrication environment. In one embodiment, shuttle (28) has a sensor which is used to determine if carrier (38) is placed on shuttle (28) within a predetermined time, allowing retraction of shuttle (28) until it is required. The present invention increases the available operative space within the fabrication environment, and provides a clean mini-environment within apparatus (20).

Abstract: Alignment of a blade (60) to an electrostatic chuck (53) is accomplished using an alignment tool (30) and an alignment pin (40) to align a port (534) in the electrostatic chuck (53) directly to a hole (602) in the blade (60). Placement of a substrate (70) in a processing chamber (50) is accomplished using a substrate handler configured with the blade (60) to place the substrate (70) accurately on the electrostatic chuck (53). The substrate (70) is then processed in the processing chamber (50) using the electrostatic chuck (53).

Abstract: A buffer film (154, 164) is formed over an underlying film (153, 162) to protect that underlying film (153, 162) from damage during a removal sequence, such as polishing. Scratches, gouging, smearing that can occur to the underlying layer (153, 162) are less likely to occur because of the presence of the buffer film (154, 164). In some embodiments, an insulating film (162) is to be protected. The buffer film (164) is formed over the insulating film (162), and the insulating and buffer films (162 and 164) are patterned. During a subsequent conductive layer polishing operation in an embodiment, most of the buffer film (164) is removed. In still another embodiment, a buffer film (154) is formed over a conductive layer (153) to protect it during "gap fill" process sequence. Although residual portions of the buffer film (154, 164) are usually removed, in some instances, those residual portions can remain if there are no significant adverse affects.

Abstract: Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Abstract: Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Abstract: Beveled clamp fingers (48) are used in an etching system. The beveled top surfaces (40) of the clamp fingers allow etching species to attack more readily the layer being etched at locations near the beveled clamp fingers (48), thereby reducing the size of halo regions (622). In other embodiments, triangular clamp fingers (78) or clamp fingers (88) with rounded top surfaces can be used.

Abstract: A process for forming via openings (24) between two aluminum-containing interconnects (15) which includes removing a veil material (22) formed during etching of an insulating layer (12), where the veil material (22) is then removed by a combination process of a first dry etch followed by an aqueous organic solvent exposure. The first dry etch uses oxygen containing and fluorine-containing gases, and is performed during the resist removal. This combination process effectively removes the veil (22), even for the heaviest of veil formation, without adversely affecting the insulating layer (12) or the underlying interconnect (15) that includes aluminum. The temperature of the aqueous organic solvent may be reduced, decreasing the amount of volatile organic compound emissions from the solvent while maintaining solvent strength.