Abstract: A substrate (10) having a central region (32) and a peripheral region (34) is processed using a chuck (40) that contacts peripheral regions (34) of the substrate but not the central region. A fabrication step is performed while the substrate (10) is on the chuck (40, 60, 70). The chuck can be used in the formation of a lithographic mask or a semiconductor device.

Abstract: Field isolation regions are formed using oxidation-resistant spacers or plugs that completely fill trenches within a semiconductor substrate prior to forming the field isolation regions. The spacers or plugs help to reduce encroachment of the field isolation regions under the spacers or plugs. The structure used as an oxidation mask for the field isolation process may include a silicon-containing member that is thicker than an overlying oxidation-resistant member. The thicker silicon-containing member may be capable of tolerating higher stress before defects in an underlying pad layer or substrate are formed.

Abstract: A chemical-mechanical polisher (10) includes a mixer section (12) that mixes components of a polishing fluid prior to introducing the polishing fluid into a polishing section (13) of the polisher (10). In one embodiment, components from feed lines (113 and 114) are combined in a manifold (121) and flowed through a static in-line mixer (123) to mix the components to form the polishing fluid. The polishing rate of the polishing fluid is relatively high because the mixing occurs near the point of use. Local concentrations of the components of the polishing fluid near a substrate (134) should be relatively uniform because the polishing fluid is mixed prior to reaching the substrate (134).

Abstract: A semiconductor device (70) includes a memory cell having a select transistor (67) and a storage transistor (65) having a relatively uniform tunnel dielectric thickness under both the floating gate (651) of the storage transistor and the select gate (671) of the select transistor (67). The select transistor (67) is adjacent to the drain region (68) for the memory cell to nearly eliminate a drain disturb problem. During programming, the control gate (652) is at a negative potential, and the drain region (68) is at a positive potential. The drain potential is sufficiently low to not degrade the tunnel dielectric layer (42) of the select transistor (67). During erase, a positive potential is applied to the control gate (652). The relatively uniform tunnel dielectric layer (42) thickness of the select transistor (67) allows for a faster operating device by increasing the read current of the memory device.

Abstract: An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

Abstract: A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Abstract: A process for dry etching a passivation layer (42) of a semiconductor device is performed such that a low radio frequency (RF) power step is used when an underlying bond pad (22) is initially exposed and a high RF power step is used after the initial exposure. The process virtually eliminates or reduces the likelihood of bond pad (22) staining, particularly when a polyimide die coat layer (72) is subsequently formed over the semiconductor device (50).

Abstract: A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.

Abstract: Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, 180) within the field isolation region (72, 152, 172, 182). The trenches (52, 54) are filled with a material (62) that is polished or etched to form the planar field isolation region (72, 74, 152, 172, 182) where the wide, planar field isolation regions (72, 152, 172, 182) include the mesa(s) (76, 150, 170, 180). Etching can be used or by polishing with minimal, if any, dishing occurs because the widths of the trenches (52, 54) are kept relatively narrow (usually no more than five microns wide). Mesas (180) within a wide, planar field isolation region (182) can form linguistic characters to better identify the part number or mask set of the device.

Abstract: A process has been developed for a post-chemical mechanical polishing cleaning/passivting step to remove slurry particles (52) and form a passivating film (64) from a portion of an interconnect material within a conductive layer (42) without attacking the interconnecting material. In one particular embodiment, a solution having a pH greater than the isoelectric point of alumina particles is exposed to the surface of an interconnect material of a conductive layer (42) to passivate a portion of the interconnect material while changing the charge of the slurry particles (52) such that they are repelled away from the surface of the substrate and removed by the cleaning solution, or other cleaning processes.

Abstract: Physical properties of alumina particles in a chemical-mechanical polishing slurry delivery loop (28) are measured using a titration technique (44). Examples of the physical properties include crystallographic phase, surface charge, and surface charge density. The physical properties are correlated to a polishing rate (46). Specification limits are generated using the correlated data (482 and 486). The specification limits are used to determine if no adjustments are required to the polishing parameters (484), if adjustments are required to polishing parameters (488) or if the slurry requires replacement (489). This process can be automated and integrated into a conventional chemical-mechanical polishing processing system (20).

Abstract: A polishing pad (34) with a poromeric structure polishes two dissimilar materials (56, 58). By using a relatively softer pad. and conditioning, relatively constant times can be used for polishing the dissimilar materials (56, 58). This makes polishing more predictable and increases the number of substrates that can be polished using a single polishing pad (34). Polishing pads (34) are typically changed when other maintenance is performed on the polisher rather than when the polishing rate becomes too low.

Abstract: Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Abstract: An integrated apparatus (10) has a dicing station (14) and a rinsing/heated drying station (16). In one embodiment, the rinsing/heated drying station (16) has a heater, such as an infrared lamp (36), or uses a heated gas. The integrating apparatus (10) helps to decrease the time between dicing and heated drying, which reduces the likelihood of corrosion of C4 bumps (64).

Abstract: A semiconductor device comprises a substrate (100), first conductive film (22 and 32) over the substrate (100), and a second conductive film (54 and 64) over the first conductive film (22 and 32). The first conductive film includes a refractory metal and nitrogen. The first conductive film has a first portion (22) that lies closer to the substrate and a second portion (32) that lies further from the substrate. The nitrogen percentage for the second portion (32) is lower than the nitrogen atomic percentage for the first portion (22). The second conductive film (54 and 64) includes mostly copper. The combination of portions (22 and 32) within the first conductive film provides a good diffusion barrier (first portion) and has good adhesion (second portion) with the second conductive film (54 and 64).

Abstract: A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.

Abstract: Large diameter probe tips (42) can be used to probe a semiconductor device (60). The probe tips (42) are oriented more perpendicular to the surface of the semiconductor device (60) and are less likely to cause damage to the semiconductor device (60). The probe tips (42) can be used with a semiconductor device (60) having elongated electrodes (64) such that a small pitch for the electrodes can be used. Small diameter probe tips (102) can also be used and have a reduced likelihood of contacting a passivation layer (36) during probing.

Abstract: A method of manufacturing a semiconductor device includes providing (51) a substrate (19), providing (52) a colloid (17) having particles held in suspension, providing (53) a reagent (18), disposing (54) the substrate (19) in a processing tool (10), combining (55) the colloid (17) and the reagent (18) to form a slurry (28), decomposing (56) the reagent (18) into a surfactant and an oxidizer, using (57) the slurry (28) to process the substrate (19) in the processing tool (10), and removing (58) the substrate (19) from the processing tool (10).

Abstract: A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.

Abstract: A shared contact structure (30) is formed to electrically connect three coupling layers (59,60,46) to each other and to an active region (33) in a semiconductor substrate (31). A first coupling layer (59) and a second coupling layer (60) are formed such that they are physically isolated from each other. The second coupling layer (60) is formed such that it is in physical contact with the active region (33). A contact opening (45) is formed, which exposes a portion of coupling layers (59, 60). The third coupling layer (46) is then formed so that it is in electrical contact with the second coupling layer (60) and the first coupling layer (59).