Abstract: A method for manufacturing an static random access memory (SRAM) cell (10) begins by manufacturing a fuse region (36) over a substrate (10). An etch stop layer (44) is formed overlying the fuse region (36) from resistor polysilicon material. In order for the fuse region (36) to be accessed and properly disabled, an opening (60) must be provided which stops on the etch stop layer (44). The etch stop (44) ensures a consistent and repeatable optimal thickness X of dielectric material above the fuse region (36) to provide for proper laser access and repair. The etch stop layer (44) therefore reduces wafer to wafer and die to die variation in thickness X and provides for a higher yield laser repair for each SRAM integrated circuit and every wafer processed using this methodology.

Abstract: A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a portion of the insulating layer (52) has been converted to form a diffusion barrier film (56). Additionally, the adhesion layer (58) is formed such that it can react with the interconnect material resulting in strong adhesion between the composite copper layer (62) and the diffusion barrier film (56) as well as allow a more continuous interconnect and via structure that is more resistant to electromigration.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.

Abstract: A data processing system has operational management registers containing attributes that are used during an application to optimize operation of the data processing system for energy, time, or costs based on the type of operation being performed by the data processing system. The data processing system can implement a different operation management technique dynamically while the program is active within the data processing system.

Abstract: A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.

Abstract: A method for forming al buried contact begins by forming an exposed contact area (22) of a substrate (10) having a surface (11). An undoped or lightly doped layer of polysilicon (32) is formed in contact with the contact area (22). A contiguous masking layer (36) is formed over one or more of the contact areas (22) to cover a contact portion of the layer (32) while exposing other portions of the layer (32). The other portions of the layer (32) are doped with dopant atoms (44). A heat cycle is used to laterally drive the dopant atoms (44) through the layer (32) and downward through a substrate surface (11) to form buried contact substrate-diffused regions (54). The resulting regions (54) have improved voltage punch-through resistance to laterally adjacent electrical diffusion regions since the masking layer (36) creates a longer thermal diffusion path for the dopant atoms which eventually reside in the regions (54).

Abstract: During an electronic circuit simulation, an input file is generated that has source code and stimulus sections. Each of the source code and stimulus sections includes linking portions that each link a portion of the source code to a portion of the stimulus sections. The input file is processed to generate object code and a stimulus file that includes linking portions. The linking portions of the stimulus file allow events to occur that are synchronized with the object code during the running of a simulation program. The linking between the stimulus file and the object code is synchronized because the stimulus file is generated from the input file that has the linking portions. The linking remains synchronized even if the input file is modified. After a simulation, masks (30, 40, 50, 60, 70) can be generated and used to form an integrated circuit (20).

Abstract: An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.

Abstract: The present invention includes a polishing pad to improve polishing uniformity across a semiconductor substrate and a method using the polishing pad. The polishing pad has a first region that is closer to the edge of the polishing pad and a second region adjacent to the first region and further from the edge of the polishing pad. The polishing pad is configured, so that the second region is thicker or less compressible compared to the first region. The polishing pad should not require significantly changing any of the equipment. Oscillating range and possibly polishing pressure may need to be changed when one of the polishing pads of the present invention is used. Other operational parameters are not expected to be substantially different from a conventional polishing pad, although slight optimization of the other operating parameters may be needed.

Abstract: One or more dielectric layers (32, 52) are formed over a ferroelectric capacitor (24) of a FENVM cell, where that the tension within the dielectric layers (32, 52) overlying the ferroelectric capacitor (24) is kept relatively low. By keeping the tension relatively low, the nonvolatile polarization of the FENVM cell is maintained during back end processing steps of a fabrication process.

Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

Abstract: A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

Abstract: A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

Abstract: A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

Abstract: An integrated circuit (10) is formed using jet vapor deposition (JVD) silicon nitride. A non-volatile memory device (11) has a tunnel dielectric layer (27) and an inter-poly dielectric layer (31) that can be formed from JVD silicon nitride. A transistor (12,13,40) is formed that has a gate dielectric material made from JVD silicon nitride. In addition, a passivation layer (47) can be formed overlying a semiconductor device (40) that is formed from JVD silicon nitride.

Abstract: Content testing (302-306) and comparator testing (312-326) of a tag section (24, 26) of a cache tag memory array is performed to confirm that the tag section (24, 26) is functional. For content testing (302-306), each tag location is tested once. Comparator testing (312-326) is performed to determine the functionality of the comparator (240, 260) of the cache tag memory array. The number of tests performed for the comparator testing is 2.times.M+2, where M is the number of bit positions in the tag location. Two of the tests are for testing the comparator's ability to identify correctly hits within the tag section (312-316). The other tests are for testing the comparator's ability to identify correctly misses within the tag section at each bit position of the tag locations (322-326).

Abstract: A protection circuit (10) for a semiconductor-on-insulator device (20) allows an electrostatic event to occur at an input/output pad (12) without adversely affecting sensitive circuits, such as MOSFETs used in digital circuits. The protection circuit (10) allows the input/output pad (12) to be biased positively and negatively with respect to two different supply potentials and to other input/output pads on the chip. A body-tied MOSFET (14) is used in the protection circuit (10) where its drain regions (38) lie outside MOSFET's closed loop gate electrode (34).

Abstract: A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.