Abstract: A chopper-stabilized amplifier having an additional differential amplifier stage for improved noise reduction. A main amplifier provides a fast AC path, while a nulling amplifier is used to zero out input offset voltages of both the main amplifier and itself. An additional differential amplifier stage precharges the nulling amplifier within an offset compensating loop to a predetermined voltage such that when the nulling amplifier is switched into the main amplifier's loop, it contributes no unwanted noise at the output of the main amplifier. An additional pair of switches activated by an additional phase of the chopper clock insert the precharge differential amplifier into the circuit at the appropriate time.

Abstract: An dispensing system is provided with a stepping plunger to minimize the air buffer at develops as material is dispensed. The stepping plunger includes a plunger body having an air passage therethrough for insertion into a syringe containing a material to be dispensed, A plunger rod having an air passage therethrough is attached at one end to the plunger body, and at the other end to an air hose. The plunger rod has a plurality of equally-spaced detents distributed along at least a portion of its the length, and a detent pin is urged into contact with at least one of said detents under spring bias. The detents are ramped to permit the plunger rod and said plunger body to move axially in one direction while being prevented from moving the opposite direction. The plunger body follows the level of material in said syringe as it is dispensed while maintaining a substantially zero air buffer in said syringe.

Abstract: A cable crosstalk measurement system provides fault diagnostic information to locates faults in addition to providing a crosstalk versus frequency function to test and troubleshoot LAN cables. In a preferred embodiment, a narrow pulse is introduced into one twisted pair of a standard LAN cable, and another twisted pair in the same cable is monitored for crosstalk signal coupling. A measurement system digitizes crosstalk signals using sequential sampling of repetitive signals to provide a waveform record that is a reconstructed equivalent time representation of a real-time crosstalk signal. A microprocessor performs a fast Fourier transform of the waveform record to provide crosstalk versus frequency information, while the waveform record is also examined for higher-than-acceptable amplitude levels to locate poor quality or faulty connectors and cables.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value.

Abstract: A pulse-based cable attenuation measurement system provides a measurement of attenuation characteristics of a cable over a wide frequency spectrum. A main test and troubleshooting unit of a cable test instrument applies stimulus signals via a selected one twisted pair in a LAN cable to a pulse receiver in a remote unit that in turn causes a pulse generator to produce a specified pulse of known amplitude and duration that is applied as a measurement pulse to a separate but adjacent twisted pair within the same bundle or cable. A measurement system analyzes the measurement pulse after it reaches the main unit, and provides attenuation versus frequency information to determine whether the amount of signal loss due to attenuation in the cable is acceptable or not.

Abstract: An impedance synthesizer includes an amplifier with selectable gain and a reference capacitor, resistor, or inductor for providing a plurality of synthesized impedance values. The voltage gain of the amplifier is controlled by a programmable multiplying digital-to-analog converter which allows the selection of a myriad of desired synthesized impedances with high precision and accuracy.

Abstract: An analog-to-digital converter utilizes low-resolution and high-resolution conversion paths for precision voltage measurements. A first conversion made using a comparatively low resolution ADC is used to predict the reference voltage to one input of a null detector that receives the input voltage on another input, and effectively magnifies the voltage difference between its inputs. In a preferred embodiment, the duty cycle of a pulse-width modulator is adjusted to precisely adjust the reference voltage to provide a nulled (or near null) reading from the null detector. A low resolution ADC then converts the voltage from the null detector, which when added to the reference voltage, yields a final reading with 18-bit to 22-bit accuracy. The preferred embodiment is implemented to read the output from a pressure transducer and employs a binary search technique to rapidly adjust the duty cycle of the pulse-width modulator.

Abstract: A dual time base, zero dead zone time domain reflectometer repetitively launches a predetermined number of stimulus pulses into a transmission system in synchronism with clock signals from a first time base, providing a measurement cycle. The duration of the launched stimulus pulses, determined by a predetermined number clock cycles from the first time base, exceeds the total propagation time of the system to be measured so that a time interval between a launch and a reflection may be measured within the launched pulse. A second time base, which has a predetermined period that differs from the period of the first time base and defines a measurement period divided into equal sub-periods, continuously produces clock signals, one or more of which may be counted during the time interval.

Abstract: A LAN cable identifier for testing and identifying copper-conductor LAN cables in conjunction with a LAN cable test instrument is provided. Series combinations of resistors and diodes allow for both resistance measurements and polarity determinations for selected pairs of conductors of the LAN cable. Resistance values are chosen to allow for identification of each combination in order to diagnose wiring errors and to identify the particular LAN cable identifier. In addition, capacitance measurements are accommodated with minimal contribution to measurement error by careful orientation of the resistors and diodes so that the diodes may be reverse biased by a d.c. bias voltage provided by the LAN cable test instrument. The reverse biased diode junctions contribute only a small amount of shunt capacitance to the measurement.

Abstract: Common mode error correction for differential amplifiers involves accurately measuring both the input and output of an amplifier using a low-leakage measurement path, and calculating common-mode gain. Two measurements are made at each node by appying two different common-mode voltages. Subtracting one set of measurements from the other eliminates voltage offset errors, and leaves a common-mode error term for gain calculation. The common-mode gain factor is stored, and thereafter, common mode error may be subtracted from measurements made by the differential amplifier.

Abstract: A voltage and resistance synthesizer includes a pulse width modulator (PWM) for synthesizing voltage and resistance values at a pair of terminals. A selector switch selects between a resistance synthesis mode, in which resistance values are synthesized from a single reference resistor, and a voltage synthesis mode, in which voltage values are synthesized from a single reference voltage. The pulse width modulator permits digital control words to be received which govern the synthesized value with 16 bit resolution. A low pass filter blocks the switching frequency components and provides a d.c. voltage which is the product of the duty cycle and the reference value.

Abstract: A digital storage oscilloscope capable of acquiring and displaying input signals over a wide range of frequencies, and automatically establishing, by menu setups or user selection, any of a number of cycles of an input signal for viewing. An input analog electrical signal is sampled at a constant rate and then stored in a fast-acquisition memory. A DSP and a CPU combine to provide an automatic time base which maintains constant width of displayed signals without changing the sampling rate. The time period of one cycle of signal is measured, and the number of digitized samples is reduced or increased by the DSP to provide constant number of samples in order to maintain a constant-width display despite any changes in the input signal frequency. Additionally, the oscilloscope horizontal display axis may be expressed in degrees per division as well as time per division.

Abstract: A dual time base, zero dead zone time domain reflectometer repetitively launches a predetermined number of stimulus pulses into a transmission system in synchronism with clock signals from a first time base, providing a measurement cycle. The duration of the launched stimulus pulses, determined by a predetermined number clock cycles from the first time base, exceeds the total propagation time of the system to be measured so that a time interval between a launch and a reflection may be measured within the launched pulse. A second time base, which has a predetermined period that differs from the period of the first time base and defines a measurement period divided into equal sub-periods, continuously produces clock signals, one or more of which may be counted during the time interval.

Abstract: A memory emulation test system is provided with a method of and system for fast functional testing of memories, such as boot ROMs, in microprocessor-based assemblies. The emulative test system includes a synchronization circuit which automatically re-arms itself and generates sync pulses on each and every UUT data access cycle to allow the UUT microprocessor to read every boot ROM memory location and collect data to be computed into a checksum or other signature to be compared with a predetermined signature representative of a correctly functioning and faultless boot ROM.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps.

Abstract: A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.