Abstract: In a multiple trace oscilloscope wherein separate traces displayed on a cathode ray tube screen are updated in succession, a random access memory is addressed by the count output of a programmable counter which increments its count each time the oscilloscope finishes updating one trace prior to updating a next trace. Data stored in the random access memory at the storage location addressed by the count is utilized to control attributes of the next trace to be updated by controlling the switching positions of attribute control switches which select the horizontal, vertical and intensity control signals controlling the appearance of each trace.

Abstract: A voltage controlled, triggered oscillator includes a NAND gate and a set of series connected triggerable delay circuits, the output of the NAND gate being fed back to one of its inputs through the delay circuits. A trigger signal is applied to another input of the NAND gate and to triggering inputs of the delay circuits. When the trigger signal is asserted, each delay circuit produces an output signal of state which tracks the state of its input signal but with a predetermined delay so that the NAND gate output oscillates with a frequency determined by the delay times of the delay circuits and the propagation time of the NAND gate. When the trigger signal is deasserted the NAND gate output is terminated and each delay circuit drives its output signal high regardless of the state of its input signal so that the oscillator may be rapidly retriggered.

Abstract: An oscilloscope having a displayed trigger indicator is provided in which triggering level, slope, and source information on displayed directly on the viewing screen adjacent corresponding waveforms. In a preferred embodiment, a vertical bar represents the triggering level range, and a marker or dot is superimposed thereon to indicate the trigger level. Slope polarity is also indicated, as is triggering source. These indicators permit the triggering point to be quickly selected and set while viewing them in relationship to corresponding waveforms, and are always on screen for convenient reference and waveform photography.

Abstract: A data compression circuit has a compression mode of operation where it determines and stores minimum and maximum values of successive sequences of applied data words and provides an output comprising a pair of data words representing the stored minimum and maximum for each sequence, offset by a selected amount. The circuit also has a transparent mode of operation where output data sequences match input data sequences.

Abstract: A differential transconductance amplifier includes two error amplifiers which provide an error correction current which linearizes a main differential amplifier. Two reference transistors coupled to the main differential amplifier provides two sets of input voltages to the two error correction amplifiers. The output currents of the main amplifier and the two error correction amplifiers are summed to produce a linearized output.

Abstract: A digital oscilloscope includes an amplifier having adjustable gain and offset for producing an output signal in response to an input signal, a triggering system for producing a trigger status signal when the amplifier output signal reaches an adjustable trigger level, and a digitizer for generating a waveform data sequence representing magnitudes of samples of the amplifier output signal acquired at various times with respect to assertion of the trigger status signal. The oscilloscope produces a waveform display on a screen according to the waveform data sequence produced by the digitizer and automatically adjusts the amplifier gain and offset, the trigger level, and the sampling rate of the digitizer so that the waveform data produced by the digitizer provides for a waveform display suitably representative of the time dependent behavior of the input signal.

Abstract: In an oscilloscope, a readout control circuit is adapted to create a horizontal cursor on an oscilloscope screen at a vertical level controlled by cursor level data generated by a microcomputer, and to cause the beam to form characters on the screen indicating a voltage represented by the vertical level of the cursor. Vertical offset and vertical gain parameters characterizing a vertical preamplifier system controlling display of a waveform are measured and utilized to determine the value of cursor level data needed to cause the readout control circuit to position the cursor on the screen to accurately reflect a selected voltage with respect to voltage magnitudes represented by points on the displayed waveform.

Abstract: A precision current generator provides an output current responsive to a reference supply voltage. The current generator comprises a voltage generator which drives the input to a buffer amplifier. The buffer amplifier output drives the bases of multiple output transistors, the collectors of which form the current outputs. The output current is not dependent upon transistor beta, junction voltage, temperature or supply voltage. The all NPN design enables the current generator to track the reference voltage at high frequencies without peaking or ringing of the output current and without voltage coupling between output devices.

Abstract: A probe for use in electrical circuit test equipment, in which a contact element is longitudinally slidable in an insulator sleeve which also contains an R-C attenuator circuit connected electrically to the contact element by an electrically conductive elastomeric material. A high impedance cable is connected electrically to the other end of the RC attenuator circuit by another piece of conductive elastomeric material. The cable connects the attenuator to another R-C circuit which, together with the attenuator, forms a voltage divider, and the attenuated signal controls an amplifier which provides a signal through a low impedance cable to a test equipment.

Abstract: A signal generator for producing a triggered output signal of digitally controlled phase and frequency includes a skewing circuit for producing an output clock signal of the same period, T, as an input, triggered reference clock signal but which is phase skewed from the reference clock signal by a phase angle, P, of 0 to 360 degrees as determined by input digital data. The skewed clock signal is frequency divided by an integer factor N, and a timing circuit counts reference clock periods to initiate frequency division a programmable delay time (J.times.T seconds) following triggering of the reference clock signal, where J and N are integers also determined by input digital data. An AND gate qualifies the frequency divided skewed clock signal with the skewed clock signal itself to produce a periodic output signal of digitally controlled frequency N/T, the first pulse of which is delayed following triggering of the reference signal by a digitally controlled interval of (T.times.J)+(P.times.T/360) seconds.

Abstract: A multiplexer samples multiple analog waveform signals to provide a sequence of input signals to an active low-pass filter. The bandwidth of the filter is determined by an input RC network having series resistance and shunt capacitance elements. As the multiplexer switches state to sample a different analog signal, the resistance elements of the filter are temporarily shorted to allow the filter input signal to rapidly charge or discharge the shunt capacitance element to a steady state voltage in response to any change in input signal voltage. The resistance elements are then unshorted to permit normal low-pass filter operation. Switch means are also provided to selectively disconnect the shunt capacitance element from the network when the resistance elements are shunted, thereby selectively widening the bandwidth of the filter to pass higher frequency input signals.

Abstract: A variable transient response control for linear integrated-circuit high-frequency amplifiers comprises a variable equivalent resistive damping network interposed in the signal transmission path, and an electronic control circuit therefor. The resistive network includes preferably Schottky diodes having low inductance and a determinable equivalent resistance in the forward conducting condition.

Abstract: A switch closure test method and apparatus is disclosed in which switch position information in the form of logic signals indicative of switch closure status of a plurality of switches is arranged in a predetermined waveform display format for simultaneous viewing.

Abstract: A frame capture circuit for use with a video camera includes an analog-to-digital converter for converting composite video to digital form and a memory for storing sequential frames of digital video. The analog-to-digital converter is connected to the memory through a summer, and the memory has an output connected to a second summer input through a feedback loop. The feedback loop includes a switch controlled by a central processing unit such that when the switch is closed, the output of the memory is a composite video data frame comprising a current plus a previous frame of data. The central processing unit closes the switch whenever an event of interest displayed on an external device falls near the end of a frame of video generated by the camera so that the entire event is captured without regard to the scanning phase of the video camera.

Abstract: An encoder circuit converts a thermometer code into an equivalent adjacent binary code wherein only a single bit is changed to minimally increment or decrement the value of the binary code. The encoder logic is grouped so that the state of any single bit of the thermometer code can affect the state of one and only one bit of the binary code whereby when any least significant thermometer code bit is at an invalid logic level, the invalid level is propagated through the encoder circuit to only a single, least significant binary code bit, without the introduction of any logical errors. The invalid binary code bit is then stabilized to a valid level by one or more latches.

Abstract: A resonance compensated unity voltage gain amplifier comprises an input stage and an output stage connected in feedback to the input stage and a series resonance circuit for compensating for the resonance of the output and input stages created by the feedback. Reactance of the series resonance circuit is adjusted to be substantially zero at the resonant frequency of the amplifier. The resonance compensated amplifier is incorporated into a gain selectable amplifier. The resistance on the output stage of the amplifier across which the input voltage is applied via the output voltage may be selectively varied to change the current gain of the amplifier.

Abstract: A high-transconductance composite PNP transistor comprises a PNP transistor and three or more NPN transistors arranged in a three-terminal configuration which behaves as a PNP transistor, and yet exhibits high beta, alpha greater than one, and transconductance approaching infinity.

Abstract: A power buffer circuit includes a power MOS device connected via a local feedback loop to a differential amplifier. The MOS device amplifies the power of an input signal to produce an output signal. The differential amplifier causes the output signal voltage to follow the input signal voltage by sensing a difference between the two voltages and generating in response a difference signal to the MOS device to change the output signal voltage level. The buffer circuit may be configured as a current source or a current sink that maintains unity voltage gain from the input to output signal. The power buffer circuit may be incorporated into a voltage regulator that maintains a remotely sensed output voltage substantially equal to a predetermined factor of a reference voltage via a second, outer feedback loop.

Abstract: A loop control system for digital processing apparatus. A dedicated storage register and associated counting register are provided for receiving a starting value representing a number of passes through a program loop. An iteration circuit is provided for receiving the value in the counting register, iterating it, and storing the new value in the same counting register with each successive pass through the loop. A detector is provided for comparing the output of the iteration circuit to a predetermined value and providing a completion signal when the new value and the ending value have a predetermined relative relationship. Control logic is provided for causing the value in the storage register to be transferred into the counting register upon the occurrence of an output signal from the detector circuit. A plurality of pairs of storage and counting registers may be provided for keeping track of the number of iterations of nested loops.

Abstract: A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.