Abstract: A charge-pump and a method are provided for conditioning the phase detector output in a phase-locked loop (PLL). The method comprises: accepting a pair of differential phase detector (PD) output signals (up/upb and dn/dnb); connecting each pair of differential PD outputs to first and second charge-pump differential sections; supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals; and, disconnecting the charge-pump differential section outputs from the loop filter inputs when the PD differential outputs (up/dn and upb/dnb) are equal. In some aspects, supplying differential charge-pump outputs (Vout+/Vout−) in response to the pair of differential PD output signals includes sourcing a first current through the first charge-pump differential section and sourcing a second current through the second charge-pump differential section. Then, the method further comprises maintaining the first current equal to the second current.

Abstract: An enhanced performance differential output amplifier and differential amplification method are provided. The amplifier comprises a first transistor to accept a single-ended input signal and supply a first output signal, and a second transistor to supply a second output signal, approximately 180 degrees out of phase from the first output signal. A first capacitor is connected between the base of the first transistor and the emitter of the second transistor. A second capacitor is connected between the emitter of the first transistor and first voltage. At least one emitter resistor, but typically two, is connected between the emitters of the first and second transistors, and a current source. The collectors of the first and second transistors are operatively connected to the first voltage, typically through resistors. The current source is connected between the emitter resistors and a second voltage (Vee) having a lower potential than the first voltage.

Abstract: A system and method are provided for measuring amplifier gain in a digital network. The method includes accepting a digital input signal; amplifying the input signal (Vin); comparing the amplified signal to dc thresholds; measuring output errors; and, calculating the amplifier gain in response to the thresholds. More specifically, accepting a digital input signal includes accepting an input signal having an amplitude. Comparing the amplified signal to dc thresholds includes comparing the amplified signal to a low threshold and a high threshold. Measuring errors includes measuring a predetermined error condition in response to the high threshold and the low threshold. Then, calculating the amplifier gain in response to the thresholds includes calculating the amplifier gain in response to the high threshold, the low threshold, and the input signal amplitude.

Abstract: A system and method are provided for compensating a comparator threshold level. The method comprises: accepting an input signal with an ac component; lowpass filtering the input signal to generate the input signal average voltage; accepting the input signal average voltage; accepting a first dc level; summing the average voltage with the first dc level; supplying a first sum as a first comparator threshold level; comparing the input signal to the first comparator threshold level; and, supplying a first comparator output signal with an ac component. In some aspects of the method, accepting a first dc level includes accepting a plurality of dc levels. Then, the average voltage is summed with each of the plurality of dc levels and supplied as a corresponding plurality of comparator threshold levels. The input signal is compared to each of the comparator threshold levels and a plurality of comparator output signals are supplied.

Abstract: A liquid metal socket test fixture system and a method for the same are provided. The system has a circuit board top surface and a plurality of wells. A liquid metal compound forms balls in the wells. An IC package having a bottom surface with electrical contacts interfaces with the liquid metal compound in the wells. In some aspects of the system, the IC package has solid ball grid array (BGA) connectors attached to the bottom surface electrical contacts, interfacing with the liquid metal compound. Alternately, the liquid metal compound interfaces directly to the IC package bottom surface contacts. A gravity-tension frame overlies the circuit board top surface. The frame provides support in the horizontal plane so that the liquid metal balls remain aligned with the IC package electrical contacts. Typically, the liquid metal compound is a mixture of approximately 24% indium and 76% gallium.

Abstract: A system and method are provided for controlling the phase of a voltage controlled oscillator output. The method comprises: accepting a plurality of VCO outputs coarsely differentiated by phase; selecting one of the VCO outputs; finely modifying the phase of the selected VCO output; and, supplying the phase modified VCO output. In one aspect, accepting VCO outputs coarsely differentiated by phase includes: accepting a first VCO output (I0); accepting a second VCO output (I1), differentiated approximately 90 degrees from the first VCO output; accepting a third VCO output (Q0), differentiated approximately 90 degrees from the second VCO output; and, accepting a fourth VCO output (Q1), differentiated approximately 90 degrees from the third VCO output. Finely modifying the phase of the selected VCO output includes modifying the selected VCO output in the range between +45 and −45 degrees. In one aspect, the output is modified in 16 discrete steps.

Abstract: A high bandwidth emitter-coupled logic (ECL) circuit is provided. The ECL circuit comprises an emitter-follower circuit with first and second transistors having collectors connected to a first power supply (Vcc), and emitters operatively connected to a second power supply (Vee2) approximately 1.5 volts less than the first power supply. The transistors receive differential input signals from an interfacing CML circuit. In some aspects, the first power supply is 3.3 volts and the second power supply is 1.8 volts. The CML circuit has an input to receive an input signal, a logic function having a level of series gated logic, first and second differential output signals responsive to the input signal and logic function, and is powered by the first power supply and a third power supply (Vee3) that is approximately equal to Vcc−(0.4+(level of series gated logic)(0.9 volts)).

Abstract: A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.

Abstract: A system and method are provided for measuring pseudorandom non-return to zero (NRZ) data rates in a communications device integrated circuit (IC). The system comprises a transition detector to sample a pseudorandom NRZ data stream and to supply a mean frequency of transitions (Fd). A probability analyzer receives the mean frequency of transitions, compares the mean frequency of transitions to a transition probability (P), and supplies a derived mean data stream rate (B), where B=Fd/P. In some aspects of the system, a gating circuit is included to supply a gate time period (Td). Then, the probability analyzer receives the gate time period, compares a mean transition count of the mean frequency of transitions to a transition probability (P), and supplies a compensated transition count (Nc), where Nc=Np/P. A system for selecting the frequency range of a VCO, for use in pseudorandom NRZ communications, is also disclosed.

Abstract: A method of applying chemical vapor deposition (CVD) copper (Cu) to integrated circuit substrates using a precursor with either a dimethoxymethylvinylsilane (dmomvs), or methoxydimethylvinylsilane (modmvs), silylolefin ligand bonded to (hfac)Cu is provided. The dmomvs ligand is able to provide the electrons of oxygen atoms from two methoxy groups to improve the bond between the ligand and the (hfac)Cu complex. The improved bond helps insure that the ligand separates from the (hfac)Cu complex at consistent temperatures when Cu is to be deposited. In situations where a precursor having a smaller molecular weight is desired, the modmvs ligand is used to provide electrons from the oxygen atom of the single methoxy group. In the preferred embodiment, water vapor is added to the volatile precursor to improve the conductivity of the deposited Cu.

Abstract: A method of forming the FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel, which extends into the drain junction region. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region.

Abstract: A Cu(hfac) allyl-derived ligand precursor has been provided. The ligand includes group consisting of alkyl, phenyl, trialkylsilane, trialkoxylsilane, halodialkylsilane, dihaloalkylsilane, trihalosilane, triphenylsilane, alkoxyl, halogen, chloroformate, cynanide, cycloalkyl, cycloalkylamine, alkyl ether, isocyanate, and pentafluorobenzene. Examples of the allyl-derived ligand precursors have proved to be stable at room temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursors, including a Cu(hfac)(allyltrimethylsilane) precursor.

Abstract: A novel motion estimation algorithm, AMESSAD (adaptive motion estimation based on statistical sum of absolute difference) is provided. The algorithm adaptively determines motion search step size based on statistical distribution of SAD (sum of absolute difference). That is, search step sizes to estimate motion in one portion of a frame are calculated using SAD values from neighboring portions of the frame. The efficient search procedure improves the implementation of motion compensation and transform based hybrid video coders, such as the H.26P and MPEG-X standard video compression. Compared with fixed step-size motion estimation, the adaptive algorithm improves motion estimation and hence overall video encoding speed. In addition, improved visual quality can be achieved in many cases because the algorithm differentiates regions with motion activity and allocates more motion estimation resources to local areas or local frames with higher motion content.

Abstract: A Cu(hfac) precursor with a substituted ethylene ligand has been provided. The substituted ethylene ligand includes bonds to molecules selected from the group consisting of C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, H, and C.sub.1 to C.sub.8 alkoxyl. One variation, the 2-methyl-1-butene ligand precursor has proved to be stable at room temperature, and extremely volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. Because of the volatility, the deposition rate of copper deposited with this precursor is very high. A synthesis method has been provided which produces a high yield of the above-described precursor.

Abstract: A method is provided for preventing the formation of oxides in the process of creating a connection aperture through an insulating layer overlying a copper conductor having a connection surface region. The method deposits at least two insulation layers over the copper connection region including a nitride dielectric material adjacent the connection region, and a second insulating material adjacent the nitride layer. An area of the second insulator is selectively removed to partially form a connection aperture extending to the nitride layer. Next, an area of the nitride layer, and any layer overlying the nitride layer, is selectively removed to form an aperture in registration with the aperture formed in the second layer. The completed connection aperture extends through the entire insulating layer to the connection region. The nitride layer protects the copper from processes that cause oxidation as the layers overlying the nitride layer are removed.

Abstract: A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region.

Abstract: A method is provided of fabricating a thin film transistor semiconductor film of polycrystalline silicon on a transparent substrate suitable for the manufacture of a liquid crystal display. A film of substantially amorphous silicon is placed on the transparent substrate. Suspended in the amorphous silicon are small silicon seed crystals. As the amorphous silicon is annealed, crystal grains, begun from the seed crystals, are formed in the resulting polycrystalline silicon. The seed crystals help regulate the annealment process, and reduce process dependence on precision deposition and heating methods. The use of seed crystals also helps ensure that crystal grains are both large and consistent in size. Large grains promote to production of TFTs with high electron mobility and uniform performance across the entire LCD. An LCD with a TFT polycrystalline film layer over a transparent substrate, formed from annealing substantially amorphous silicon with suspended seed crystals, is also provided.

Abstract: A method of enhancing copper adhesion to a substrate includes preparing a single-crystal silicon substrate; forming integrated circuit components on active areas of the substrate; metallizing the integrated circuit components, including metallizing a first copper layer by low-rate CVD, and metallizing a second copper layer by high-rate CVD; and finalizing construction of the structure.

Abstract: A method for rapid thermally annealing a thin amorphous film on a transparent substrate with the use of a radiation absorption film is provided. Unlike a transmissive silicon thin film, or transparent substrate, the metal absorptive film has excellent radiation absorption characteristics. When a radiation absorption layer is added to the substrate it is possible to rapidly anneal an amorphous silicon film with convention IC process radiation lamps. The metal absorption film also acts to conduct the heat to the amorphous silicon. The control provided by the choice of metal material, metal thickness, the oxidation of the metal surface, and the heat and duration of the RTA process provide unique opportunities to control the crystallization process. Polysilicon made by the above-described method has the potential of high electron mobility and low production costs. A thin-film structure for use in a TFT, made through the above-described method, is also provided.

Abstract: A method of forming a FEM cell semi-conductor structure includes forming a device area for the ferroelectric memory (FEM) gate unit on a silicon substrate. Appropriate impurities are implanted into the device area to form conductive channels, for use as a source junction region, a gate junction region and a drain junction region. A FEM cell includes a FEM gate unit formed on the substrate. A gate junction region is formed between the source junction region and the drain junction region for the FEM gate unit on the FEM gate unit device area, which FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer, and an upper metal layer. A shallow junction layer is formed between the FEM gate unit and the gate junction region, as another conductive channel. The FEM gate unit is spaced apart from the source region and the drain region, as is the conductive channel between the FEM gate unit and the gate junction region.