Patents Represented by Attorney, Agent or Law Firm Gerald Maliszewski
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Patent number: 8179924Abstract: A system and method are provided for synchronizing a programmable timer time base and an external time signal. The method either accepts or supplies an external time signal (e.g., IEEE 1588) at an external interface, links a synchronized time base to the external time signal, and clocks a channel time base with the synchronized time base. Then, a timer channel can be used to perform programmable timer functions in response to the channel time base. Some programmable timer functions include input capture, output compare, quadrature decoding, pulse measurement, frequency measurement, and pulse width modulation (PWM) functions. In one aspect, accepting the external time signal at the external interface includes detecting a packet with a time value. In another aspect, the method uses the channel to detect an event at a channel external interface, and compares the channel time base counter value with an expected value to modify the synchronized time base.Type: GrantFiled: May 31, 2006Date of Patent: May 15, 2012Assignee: Applied Micro Circuits CorporationInventor: Damien Latremouille
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Patent number: 8175207Abstract: An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing Q-bit values sampled by the varied delay Q clock. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signal are generated.Type: GrantFiled: August 11, 2009Date of Patent: May 8, 2012Assignee: Applied Micro Circuits CorporationInventors: Viet Linh Do, Wei Fu
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Patent number: 8176282Abstract: A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain ID is cross-referenced to a cache partition identified by partition bits. An index is derived from the physical memory address, and a partition index is created by combining the partition bits with the index. A processor is granted access (read or write) to an address in cache defined by partition index.Type: GrantFiled: April 6, 2009Date of Patent: May 8, 2012Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Patent number: 8161250Abstract: Aspects of the present invention comprise systems and methods for protecting multi-threaded access to shared memory. Some aspects provide higher data concurrency than other methods. Some aspects relate to methods and systems that provide access to data for all threads during the first phases of one thread's write operation. Some aspects provide all threads access to a particular data unit until one thread enters the commit phase of the write operation. Some aspects manage a computing data resource such that, when a thread enters the commit phase, all pending read requests are fulfilled, all pending write requests are allowed to proceed to commit phase at which point they are blocked, all new read and write requests are blocked and the commit phase is completed by updating the target data and releasing the blocked requests. Some aspects provide improved concurrency by performing reduced cross-thread interference. Some aspects may be implemented at any level from hardware to high-level languages.Type: GrantFiled: May 20, 2009Date of Patent: April 17, 2012Assignee: Sharp Laboratories of America, Inc.Inventor: Harold Scott Hooper
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Patent number: 8160057Abstract: Systems and methods are provided for multi-channel ITU G.709 optical transport network (OTN) communications. The transmission method accepts an ITU G.709 OTN frame including an OTU overhead (OH) section and an ODU section. A forward error correction (FEC) parity section with a training signal is appended to the ITU G.709 OTN frame, to create a training-enhanced (TE) OTN frame. All, or a portion of the TE OTN may be buffered in a tangible memory medium in preparation for striping. The training-enhanced OTN frame is then striped into n parallel streams, and n TE_OTN-PFs (Parallel Frames) are supplied.Type: GrantFiled: June 30, 2008Date of Patent: April 17, 2012Assignee: Applied Micro Circuits CorporationInventors: Francesco Caggioni, Omer Acikel, Keith Conroy
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Patent number: 8155134Abstract: A Queue Manager (QM) system and method are provided for communicating control messages between processors. The method accepts control messages from a source processor addressed to a destination processor. The control messages are loaded in a first-in first-out (FIFO) queue associated with the destination processor. Then, the method serially supplies loaded control messages to the destination processor from the queue. The messages may be accepted from a plurality of source processors addressed to the same destination processor. The control messages are added to the queue in the order in which they are received. In one aspect, a plurality of parallel FIFO queues may be established that are associated with the same destination processor. Then, the method differentiates the control messages into the parallel FIFO queues and supplies control messages from the parallel FIFO queues in an order responsive to criteria such as queue ranking, weighting, or shaping.Type: GrantFiled: September 29, 2007Date of Patent: April 10, 2012Assignee: Applied Micro Circuits CorporationInventors: Mark Fairhurst, John Dickey
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Patent number: 8153482Abstract: A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.Type: GrantFiled: September 22, 2008Date of Patent: April 10, 2012Assignee: Sharp Laboratories of America, Inc.Inventor: Mark Albert Crowder
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Patent number: 8149031Abstract: A charge pump includes a reference charge pump with an input interface to accept a phase detector signal and a duty-cycle feedback signal, and an output to supply a control voltage. A replica charge pump accepts the phase detector signal supplies the duty-cycle feedback signal. If the reference charge pump source current (Ip) becomes mismatched with the sinking current (In), non-equal Tn and Tp time periods may result. The phase detector accepts reference and data signals having a steady state offset error and supplies a non-50% duty cycle square wave phase detector signal. The replica charge pump supplies a duty-cycle feedback signal to the reference charge pump responsive to the non-50% duty cycle phase detector signal and the reference charge pump equalizes the source and sink currents. When the phase detector measures reference and data signals fully orthogonal in phase, it supplies s 50% duty cycle signal.Type: GrantFiled: September 8, 2010Date of Patent: April 3, 2012Assignee: Applied Micro Circuits CorporationInventor: Hesam Amir Aslanzadeh
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Patent number: 8145978Abstract: A system and method are provided for efficiently initializing a redundant array of independent disks (RAID). The method monitors host write operations and uses that information to select the optimal method to perform a parity reconstruction operation. The bins to which data access write operations have not occurred can be initialized using a zeroing process. In one aspect, the method identifies drives in the RAID array capable of receiving a ‘WriteRepeatedly’ command and leverages that capability to eliminate the need for the RAID disk array controller to provide initialization data for all disk array initialization transfers. This reduces the RAID array controller processor and I/O bandwidth required to initialize the array and further reduces the time to initialize a RAID array. In a different aspect, a method is provided for efficiently selecting a host write process for optimal data redundancy and performance in a RAID array.Type: GrantFiled: June 29, 2011Date of Patent: March 27, 2012Assignee: Summit Data Systems LLCInventors: Christophe Therene, James R. Schmidt
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Patent number: 8138801Abstract: A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut—1). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut—2). The selected frequency source is compared to fpdOut—1 and fpdOut—2 signals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.Type: GrantFiled: September 28, 2010Date of Patent: March 20, 2012Assignee: Applied Micro Circuits CorporationInventors: Viet Do, Simon Pang
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Patent number: 8138627Abstract: A system and method are provided for managing network-connected devices in peak power periods. The method establishes a network of connected devices, identifying a first device in the network as an off-peak device, and a second device as a peak device. If a peak power warning signal is detected, the off-peak device is disabled, but not the peak device. Any job destined for the off-peak device from a source device is relayed to the peak device and processed by the peak device. If the job destined for the off-peak device is a job format associated with the off-peak device, relaying the job to the peak device may further include the operation of converting the job to a job format associated with the peak device. In one aspect, a destination change message is sent to the source device, indicating the location of the peak device processing the job.Type: GrantFiled: March 30, 2009Date of Patent: March 20, 2012Assignee: Sharp Laboratories of America, Inc.Inventor: Andrew Rodney Ferlitsch
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Patent number: 8140647Abstract: A method and system are provided for accelerated data uploading to a remote service device destination. An on-line (third party) storage device receives an upload request message from a network-connected client device. A unique first descriptor in a descriptor field of the upload request message is accessed and compared to a list of descriptors maintained by the on-line storage device. If the accessed first descriptor is on the list, a first file is read that is stored in the on-line storage device and associated with the accessed first descriptor. The first file is then sent to a network-connected remote service device.Type: GrantFiled: November 17, 2009Date of Patent: March 20, 2012Assignee: Applied Micro Circuits CorporationInventor: Loic Juillard
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Patent number: 8140613Abstract: Presented herein are systems, methods, devices for imaging device event notification administration and subscription.Type: GrantFiled: April 2, 2011Date of Patent: March 20, 2012Assignee: Sharp Laboratories of America, Inc.Inventors: Joey P. Lum, Uoc H. Nguyen, Boguslaw Ludwik Plewnla, Lena Sojian
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Patent number: 8135886Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.Type: GrantFiled: February 28, 2011Date of Patent: March 13, 2012Assignee: Net Navigation Systems, LLCInventors: Andrew Li, Michael Lau, Asad Khamisy
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Patent number: 8133822Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.Type: GrantFiled: August 22, 2008Date of Patent: March 13, 2012Assignee: Sharp Laboratories of America, Inc.Inventors: Jiandong Huang, Pooran Chandra Joshi, Hao Zhang, Apostolos T. Voutsas
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Patent number: 8135281Abstract: A Free Space Optics (FSO) connector is provided with a method for interfacing to an electronic circuit card electrical connector via the FSO connector. The method transceives electrical signals via an electronic circuit card electrical connector. Using an FSO connector, the method converts between electrical signals and optical signals, and transceives optical signals via free space. In one aspect, the optical signals are initially received via free space along a first axis, and reflected along a second axis. Further, the optical signals may be initially transmitted along the second axis and reflected into free space along the first axis. In another aspect, the optical signals are transceived in a plurality of directions in free space. For example, optical signals may be transmitted and received in four mutually-orthogonal axes.Type: GrantFiled: April 11, 2009Date of Patent: March 13, 2012Assignee: Applied Micro Circuits CorporationInventors: Igor Zhovnirovsky, Subhash Roy, Keith Conroy
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Patent number: 8125979Abstract: Systems and methods are provided for multi-channel ITU G.709 optical transport network (OTN) transmission and receiving. The transmission method accepts a canonical ITU G.709 OTN frame including an OTU overhead (OH) section, an ODU section, and a forward error correction (FEC) parity section. A training signal wrapper is added to the ITU G.709 OTN frame, and at least a portion of a training-enhanced (TE) OTN frame is buffered in a tangible memory medium in preparation for striping. The method stripes the training-enhanced OTN frame into n parallel streams to supply n TE_OTN-PFs (Parallel Frames) at an output.Type: GrantFiled: July 8, 2008Date of Patent: February 28, 2012Assignee: Applied Micro Circuits CorporationInventors: Francesco Caggioni, Omer Acikel, Keith Conroy
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Patent number: 8121242Abstract: A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.Type: GrantFiled: February 18, 2009Date of Patent: February 21, 2012Assignee: Applied Micro Circuits CorporationInventors: Viet Linh Do, Mehmet Mustafa Eker, Simon Pang
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Patent number: 8120802Abstract: A system and method are provided for securely accessing imaging job resources in a printing device. The method initially downloads a restricted software resource to a printing device. That is, the resource is restricted to use by a user group. As differentiated from factory installed software, or field upgrades, the restricted software resource is stored in a user-accessible memory, such as non-volatile storage (e.g., RAM). Subsequently, an imaging job is accepted for processing. The imaging job is verified to be associated with the user group. Subsequent to verification, access is permitted to the restricted software resource, and the imagining job is processed using the restricted software resource.Type: GrantFiled: December 6, 2006Date of Patent: February 21, 2012Assignee: Sharp Laboratories of America, Inc.Inventors: Roy K. Chrisop, Lena Sojian, Andrew Rodney Ferlitsch
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Patent number: 8113721Abstract: An off-axis misalignment compensating fiber optic cable plug is provided. The plug has a cable interface to engage a fiber optic core end, where the fiber optic core has a cross-sectional area. The plug also includes a lens having a first surface to transceive an optical signal with a jack. The first surface has a cross-sectional area at least 30 times as large as the core cross-sectional area. The lens has a second surface to transceive optical signals with the fiber optic line core end. In one aspect, the lens has an axis and the lens first surface is convex with a radius of curvature capable of receiving an optical signal beam with a beam axis of up to ±2 degrees off from the lens axis. Even 2 degrees off-axis, the lens is able to focus the beam on the fiber optic line core end.Type: GrantFiled: October 19, 2009Date of Patent: February 14, 2012Assignee: Applied Micro Circuits CorporationInventors: Igor Zhovnirovsky, Subhash Roy