Abstract: A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.

Abstract: A system and method are provided for selectively functionalizing a transducer microarray. The method provides a microarray including a field of transducers exposed to a shared local environment. A difference in the pH associated with the transducers is created. As a result, functional molecules are selectively bound to transducers in response to the pH associated with the transducers. In one aspect, the micro-array also provides a field of transducer pH-generating electrodes, one pH-generating electrode for each transducer, and a counter electrode. The difference in pH associated with the transducers is created by selectively applying a voltage potential between pH-generating electrodes and the counter electrode, to create a difference of pH in regions adjacent to the transducers.

Abstract: Provided are a system and method of estimating channels for a plurality of multicarrier signals in a wireless receiver. A receiver accepts a plurality of multicarrier signals, transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies and nominally orthogonal reference signals. For each multicarrier signal, a reference signal is recovered including a plurality of adjacent subcarrier frequencies carrying predetermined symbols. A channel estimate is found across the plurality of adjacent subcarrier frequencies, for each multicarrier signal channel, by compensating for a loss of orthogonality between reference signals, in response to assuming a linear phase rotation for each channel across the plurality of adjacent reference signal subcarriers, and a constant amplitude for each channel across the plurality of adjacent reference signal subcarriers.

Abstract: A system and method are provided for framing messages in a forward error correction (FEC) structure for data streams encoded with redundant signal conditioning information. The method accepts signal conditioning-encoded words at a first bit rate, and eliminates redundant information in the signal conditioning-encoded words, creating N reduced-bit words of k bits. The k-bit words are mapped into a payload field of N*(k/p) p-bit words. Overhead (OH) and FEC parity fields are generated, and a frame is created including the OH field, payload field, and FEC parity field. The bit values in the frame are then pseudorandomly scrambled and the scrambled frame is transmitted at the first bit rate. A system and method are also presented for recovering the signal conditioning-encoded words from an FEC frame.

Abstract: A system is provided for maintaining imaging device (IDev) accounting data. A primary accounting server (PAS) sends messages to an imaging device (IDev) and to a lightweight accounting back-up server (LABS). The PAS receives messages from the IDev and updates a primary IDev activity log (PIAL). The IDev receives messages from the Primary server and a LABS in communication with the IDev. The LABS sends and receives messages and data from the IDev and from the PAS. The IDev sends a record of its activity to the PAS when the PAS is available, and the PAS maintains a primary IDev activity log (PIAL). The IDev sends a record of its activity to the LABS when the PAS is not available and the LABs maintains a temporary IDev activity log (TIAL). The PAS updates the PIAL with the TIAL data after a period of unavailability.

Abstract: A system and method are provided for zeroing pre and post-tap settings in a link partner using a plurality of voltage gain taps. The method provides a link partner (LP) transmitter. A network-connected local device (LD) selects an LP pre-tap or post-tap. The LD also chooses a zero gain setting for the selected LP tap. In a first iteration, the LD directs the LP to decrease the difference between the selected tap gain setting and the zero setting by 1 step. If a limit signal is not received by the LD, the LP is directed to maximally increase the center tap gain setting until a limit signal is received. The iterations are continued until a limit signal is returned in response to the LD directing the LP to decrease the difference between the selected tap gain setting and the zero setting.

Abstract: A method is provided for temporarily disabling printer job language (PJL) commands in a printer device. In a printer device, an electronically formatted print job is accepted with embedded PJL commands. The method parses the print job, and in doing so, differentiates a first PJL command and a PJL disable command. The print job is automatically processed (as is conventional), while temporarily ignoring the first PJL command in response to the PJL disable command. In one aspect, the printer differentiates the first PJL command enveloping the print job, and the PJL disable command enveloping the first PJL command envelope.

Abstract: A plasmonic display device is provided that uses physical modulation mechanisms. The device is made from an electrically conductive bottom electrode and a first dielectric layer overlying the bottom electrode. The first dielectric layer is a piezoelectric material having an index of expansion responsive to an electric field. An electrically conductive top electrode overlies the first dielectric layer. A first plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the top and bottom electrodes and in contact with the first dielectric layer. In one aspect, the plasmonic particles are an expandable polymer material covered with a metal coating having a size responsive to an electric field.

Abstract: A system and method are provided for using disparity measurements to control the adjustment of a data slicer threshold. The method receives a serial stream of pseudorandom digital data signals having an average DC value, and compares data signal amplitudes to a slicer threshold value. In response to the slicer threshold value comparison, data signal “1” and “0” values are determined. A first sum of determined “1” values is created, and a second sum of determined “0” values is created. The slicer threshold value is adjusted in response to the comparison of the first and second sums. More explicitly, the slicer threshold value is adjusted to make “1” values more likely in response to the second sum being larger than the first sum. Alternately, the slicer threshold value is adjusted to make “0” values more likely in response to the second sum being smaller than the first sum.

Abstract: A system and method are provided for recovering from print assembly failure in a printer with printed medium assembly capabilities. The method generates a first print set including a plurality of physical medium sheets, and stores the first print set of a first interim stacker. A second print set is generated including a plurality of physical medium sheets. Sheets are accessed sheets from the first interim stacker and assembled with sheets from the second print set, generating a final print set with a plurality of sheets in a first order. The final print set is stored in an output stacker. In the event of a first print set failure, first print set replacement sheets are generating. In one aspect, generating the final print set includes directly merging first print set replacement sheets (bypassing the interim stacker) with sheets from the second print set.

Abstract: A system and method are provided for appending element files to a print container in a multifunctional peripheral (MFP) device. The method accepts a first element file and a print container including a second element file. Examples of element files other print containers, fixed documents, application-specific documents, page description language (PDL) documents, extensible markup language (XML) paper specification (XPS) fixed documents, facsimile documents, and scanned documents. The method modifies the print container to include the second element file and the first element file preserved as separate entities, and stores the modified print container in a tangible memory medium.

Abstract: A system and method are provided for generating virtual lane (VL) forward error correction (FEC) overhead (OH) in a communication multi-lane distribution (MLD) protocol transmitter, and for recovering data words from virtual lanes with FEC OH in an MLD protocol receiver. The transmission method accepts an Optical Transport Network (OTN) frame with n consecutively ordered payload chunks of data words, at a first data rate. Each payload chunk is assigned to a virtual lane data word (VLDW) in an MLD frame of n consecutively ordered VLDWs. The assignment order of payload chunks to VLDWs is rotated at the start of each MLD frame. VLDWs are joined into VLDW groups, where each VLDW group includes at least one VLDW. FEC blocks are calculated for VLDWs, creating ordered VL codewords (VLCWs). Then, the VLCWs are multiplexed to maintain a consistent assignment of VLCW order to physical transmission lanes and transmitted.

Abstract: A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max). The aggressor net delay range at least partially overlaps the victim net delay range. Without increasing the value of Vmax (critical path timing), the first circuit victim net delay range is shrunk, thereby minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.

Abstract: A method and system are provided for aligning the optic port of a device having a Free Space Optics (FSO) connector. In a link device with an FSO connector, a controller determines that an optic port alignment procedure is required. A lens is set to an initial wide beam dispersion mode, and a mirror is set to an initial position angle. Note: the lens and mirror may be the FSO connector receive path or transmit path. An optical signal is communicated at a first low baud rate, and the first baud rate communications are optimized by iteratively adjusting the mirror and narrowing the lens focus. Then, an optical signal is communicated at a second baud rate, faster than the first baud rate, and the second baud rate communications are optimized by iteratively adjusting the mirror and narrowing the lens focus.

Abstract: System and methods are provided, in an Optical Transport Network (OTN), for communicating asynchronous Tributary Slots (TSs) via a synchronous Optical Payload Transport Unit of level k (OTUk) interface. The transmission method accepts a plurality of TSs at a corresponding plurality of asynchronous data rates. The TSs are mapped, using a tangible memory medium, into pseudo-Optical channel Data Tributary Unit (ODTU) frames synchronized to a common clock. Then, the synchronized pseudo-ODTU frames can be interleaved into an OTUk frame, without the need of a phase-locked loop (PLL) or buffering.

Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).

Abstract: A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain.

Abstract: A system and method are provided for identifying the data rate of an input signal in a communications receiver. The method supplies a candidate frequency from a list of potential input data rate frequencies. A first test is performed, attempting to phase-lock a coded input data signal using a reference signal at the candidate frequency. If the input signal is phase-locked, a second test is performed of monitoring a phase detector output signal for the occurrence of a phase-lock interrupt. If a phase-lock interrupt is not monitored, a third test is performed of harmonic band detection. In response to passing the first, second, and third tests, the candidate frequency is selected as the reference frequency and the input data signal is decoded. If the first, second, or third test is failed, an alternate candidate frequency is supplied from the list and the tests are repeated, beginning with the first test.

Abstract: An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. An I clock and a function-controlled oscillation cycle phase delay Q clock are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with the function-controlled varied phase delay Q clock, creating digital I-bit and varied phase delay Q-bit values, respectively. The values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing varied phase delay Q-bit values with I-bit values. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signals are generated.

Abstract: An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase.