Abstract: Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.

Abstract: A method of dynamically generating a presentation sequence from a plurality of authored presentation documents includes the steps of receiving the plurality of authored presentation documents from a plurality of data sources; applying the plurality of authored presentation documents to a set of presentation rules; and generating the presentation sequence in response to the applying step.

Abstract: The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection level of the write logs is equal to or greater than the data protection level of the storage units. Moreover, the write logs have metadata describing contents of the write logs, wherein the metadata include a sequence number identifying the age of the metadata. Each of the data blocks is a member of a parity group having addressable data blocks and first parity blocks. The addressable data blocks have at least one host data block and at least one associated data block.

Abstract: Disclosed are embodiments of a radio frequency identification (RFID) authentication system and an associated authentication methodology. The embodiments incorporate an identification device (e.g., an identification badge, a key fob, etc.) with an embedded RFID tag. The embedded RFID tag is associated with a specific user and stores a private key generated as part of a public key-private key encryption scheme. The private key is read by an RFID reader and used to decode public key encrypted data stored within or accessible by a computer system (e.g., a desktop computer system, a laptop computer system, a personal digital assistant (PDA), a digital fax machine, wireless telephone, etc.). Thus, the embodiments provide a portable way to use public key-private key encryption scheme data anywhere using RFID technology.

Abstract: Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal.

Abstract: Provided is a technology capable of managing the processing status of hardware blocks by a less number of registers.

Abstract: Disclosed is a method of extracting informative phrases from a full corpus of documents. An index of phrases contained in the full corpus of documents is built. Then, a user specifies a subset of text to analyze. The subset may be defined as: (1) all paragraphs or sentences containing terms selected as defining a subject; (2) all documents in a category; (3) all documents written within a date range; and/or (3) all documents matching a Boolean query of terms. Once the subset is specified, it is analyzed to extract informative phrases. Specifically, the index is queried to retrieve all phrases within the subset. The number of times each of the phases occurs in the subset and in the corpus is counted. Each phrase contained in the subset is scored according to informativeness based on a comparison of a likelihood that the phrase occurs in the subset and a likelihood that the phrase occurs in the corpus as a whole.

Abstract: Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.

Abstract: Disclosed are embodiments of a method and an associated computer program product for finding the statistical bounds, the corresponding parameter corners and the probability density function of one or more performance targets for a circuit without requiring Monte Carlo simulation runs. To accomplish this, a joint probability density function for independent parameters that affect the performance target can be constructed. Then, based on the joint probability density function, the statistical bounds of the performance target can be found by constructing an equal-probability-density surface of the joint probability density function and solving a constrained optimization problem on that equal-probability-density surface. Once the statistical bounds are determined, the corresponding parameter corners for the performance target can also be determined.

Abstract: A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating stripes of air gaps and dielectric that are orthogonal to a uni-directional metal wiring layout; parallel alternating stripes of air gaps and dielectric that are diagonal to either a uni- or bi-directional metal wiring layout; and a checkerboard pattern of air gaps and dielectric that crosses either a uni- or bi-directional metal wiring layout are easily formed by conventional photolithography and provide a comparatively uniform reduction in parasitic capacitance between the wires and the surrounding materials, when about one-half of a total length of the metal wiring layout is disposed within the air gaps.

Abstract: A method executes computerized instructions within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics.

Abstract: A method of automatically matching schemas begins by extracting schemas from sources and targets. Then, source and target attributes are extracted from the schemas. Each source schema will have multiple source attributes and each target schema will also have multiple target attributes. The source attributes and the target attributes are presented as nodes in a bipartite graph. This bipartite graph has edges between nodes that are related to each other. A plurality of similarity scores are defined between each set of related nodes. Each of the similarity scores is based on a different context-specific cue of the attributes that the nodes represent. These context-specific cues can comprise lexical name, semantic name, type, structure, functional mappings, etc. An overall weight is computed for each edge in the bipartite graph by combining the similarity scores of each set of nodes that form an edge.

Abstract: A method forms a structure has a substrate having at least one semiconductor channel region, a gate dielectric on the upper surface of the substrate over the semiconductor channel region, and a gate conductor on the gate dielectric. Asymmetric sidewall spacers are located on the sidewalls of the gate conductor and asymmetric source and drain regions are located within the substrate adjacent the semiconductor channel region. One source/drain region is positioned closer to the midpoint of the gate conductor than is the other source/drain region. The source and drain regions comprise a material that induces physical stress upon the semiconductor channel region.

Abstract: Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

Abstract: Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time.

Abstract: Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure.

Abstract: A magnetic character recognition (MICR) encoding device has a treatment station that applies a chemical treatment to the blank region as the sheets pass along the sheet path that compensates for a fuser release agent that a marking station uses. If blank region was not treated, the fuser release agent might detrimentally affect the printing of the additional magnetic ink markings. In order to properly align the blank region with the treatment station, the embodiments herein include at least one read head that is positioned before the treatment station along the sheet path. A controller analyzes the signals from the read head to determine whether the magnetic ink markings are aligned with the treatment station.

Abstract: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

Abstract: Disclosed are embodiments of an electroplating system and an associated electroplating method that allow for depositing of metal alloys with a uniform plate thickness and with the means to alter dynamically the alloy composition. Specifically, by using multiple anodes, each with different types of soluble metals, the system and method avoid the need for periodic plating bath replacement and also allow the ratio of metals within the deposited alloy to be selectively varied by applying different voltages to the different metals. The system and method further avoids the uneven current density and potential distribution and, thus, the non-uniform plating thicknesses exhibited by prior art methods by selectively varying the shape and placement of the anodes within the plating bath. Additionally, the system and method allows for fine tuning of the plating thickness by using electrically insulating selectively placed prescribed baffles.