Abstract: Disclosed is a storage management framework that integrates corrective action plans output from multiple different types of planning tools, sorts the different corrective action plans based on utility and risk values and outputs a time-based schedule for implementing one or more of the corrective action plans to resolve identified current and anticipated workload service level objective (SLO) violations.

Abstract: Methods and devices detect a first lateral measure of an edge of a belt loop supported by rollers within an apparatus using a first sensor to find an amount of misalignment of the edge of the belt loop relative to a known alignment position. The first sensor is positioned at a first location within the apparatus. The methods and devices also detect a second lateral measure of the edge of the belt loop within the apparatus relative to the known alignment position using a second sensor. The second sensor is positioned at a second location within the apparatus that is different than the first location. The methods and devices use a processor to determine the non-linear shape of the edge of the belt loop based on the second lateral measure of the edge of the belt loop detected by the second sensor. The methods and devices correct the amount of misalignment detected by the first sensor based on the non-linear shape of the edge of the belt loop to generate a corrected misalignment value, using the processor.

Abstract: A method and system have a media path having moving devices that move a media sheet in a processing direction. At least two elongated sensors within the media path are positioned diagonally relative to the processing direction. The media sheet has two lateral sides, a leading edge, and a trailing edge. A registration controller is operatively connected to the media path and to the elongated sensors. Each of the elongated sensors simultaneously identifies: a location of one of the lateral sides of the media sheet, such that a combination of the elongated sensors simultaneously outputs at least two lateral measures of locations of the lateral sides of the media sheet; and at least one measure leading edge or at least one measure of the trailing edge of the media sheet.

Abstract: Disclosed are embodiments of a system and method for treating a printed flexible book cover prior to book binding. In the embodiments, a liquid (e.g., water or a water-oil solvent mixture) can be applied (e.g., by a liquid applicator, such as a spray nozzle, sponge, brush, etc.) to the spine portion only of the book cover so that it pools on the surface. After a predetermined amount of time, the liquid can be removed (e.g., by a liquid remover, such as a vacuum, blower, heater, etc.). Allowing the spine portion of the book cover to soak in the liquid for this predetermined amount of time ensures that the liquid saturates the spine portion. Saturating the spine portion of the book cover alters the surface structure and, thereby enhances adhesion of an adhesive material (e.g., glue or tape) during a subsequent book binding process even in the presence of fuser oil.

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract: A method and system provides one or more product type descriptions, and constructs a map between the sub-conditions of the product type descriptions and constructs in a Web Ontological Language (OWL). The method converts the product type description rules into new OWL classes by creating a new OWL class for each corresponding rule; adding the new OWL class to the OWL ontology; for each condition of the corresponding rule, extracting sub-conditions; for each the sub-condition extracted; creating new constructs for the new OWL class using the map; and adding new class restrictions to the new OWL class, wherein each of the new class restrictions relates to a corresponding condition of the corresponding rule.

Abstract: A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches.

Abstract: Disclosed in a method and structure for searching data in databases using an ensemble of models. First the invention performs training. This training orders models within the ensemble in order of prediction accuracy and joins different numbers of models together to form sub-ensembles. The models are joined together in the sub-ensemble in the order of prediction accuracy. Next in the training process, the invention calculates confidence values of each of the sub-ensembles. The confidence is a measure of how closely results form the sub-ensemble will match results from the ensemble. The size of each of the sub-ensembles is variable depending upon the level of confidence, while, to the contrary, the size of the ensemble is fixed. After the training, the invention can make a prediction. First, the invention selects a sub-ensemble that meets a given level of confidence.

Abstract: A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.

Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.

Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract: Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

Abstract: A lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) with a high drain-to-body breakdown voltage (Vb) incorporates gate structure extensions on opposing sides of a drain drift region. The extensions are tapered such that a distance between each extension and the drift region increases linearly from one end adjacent to the channel region to another end adjacent to the drain region. In one embodiment, these extensions can extend vertically through the isolation region that surrounds the LEDMOSFET. In another embodiment, the extensions can sit atop the isolation region. In either case, the extensions create a strong essentially uniform horizontal electric field profile within the drain drift. Also disclosed are a method for forming the LEDMOSFET with a specific Vb by defining the dimensions of the extensions and a program storage device for designing the LEDMOSFET to have a specific Vb.

Abstract: Disclosed is a field effect transistor (FET), in which ohmic body contact(s) are placed relatively close to the active region. The FET includes a semiconductor layer, where the active region and body contact region(s) are defined by a trench isolation structure and where a body region is below and abuts the active region, the trench isolation structure and the body contact region(s). A gate traverses the active region. Dummy gate(s) are on the body contact region(s). A contact extends through each dummy gate to the body contact region below. Dielectric material isolates the contact(s) from the dummy gate(s). During processing, the dummy gate(s) act as blocks to ensure that the body contact regions are not implanted with source/drain dopants or source/drain extension dopants and, thereby to ensure that the body contacts, as formed, are ohmic. Also disclosed are an integrated circuit structure with stacked FETs, having such ohmic body contacts, and associated methods.

Abstract: A method stores serial numbers within memories of customer replaceable units that are used within printing devices. When one or more of the customer replaceable units are replaced, the method causes the printing devices to output to a computer the serial numbers of the customer replaceable units that are replaced. The method then analyzes the serial numbers using the computer to determine which specific customer replaceable unit was used within a specific printing device.

Abstract: Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors.

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).

Abstract: A method and system for skew detection is provided using connected components analysis. The methodology includes extracting connected components corresponding to the image and analyzing the image based on said connected components for determining skew of the image.

Abstract: Systems and methods maintain at least one point of interest data file within a computer-readable storage medium and automatically identify a current user location of a user based on a geographic positioning feature of a portable electronic device that is maintained within a first predetermined distance from the user. The systems and methods automatically compare the current user location with the point of interest data file to identify whether the user is located within a second predetermined distance of a point of interest maintained within the point of interest data file. If the user is within the second predetermined distance of a point of interest, the systems and methods automatically create a user status data file. The user status data comprises data identifying that the user is currently at the point of interest.

Abstract: A proxy directory server discovers the topology of distributed directory server immediately after starting up and before accepting client requests. Immediately after starting up, the proxy server executes queries to extract the structured data corresponding to directory distribution information from the distributed directory servers. Dynamic topology reconfiguration of the distributed directory is achieved by any dynamic configuration changes made to the topology information directly at the proxy during operation being propagated by means of directory update operations to the distributed directory servers.