Abstract: A system for utilizing tab attributes includes a communications component, a user interface component, a ticket generation component, and a job submissions component. The communications component operatively communicates at least one print document. The user interface component operatively communicates user data including tab data. The ticket generation component generates a ticket including at least one tab attribute. The ticket generation component communicates with the communications component and the user interface. The ticket generation component receives the user data from the user interface component and the ticket generation component receives the at least one print document from the communications component. The ticket is associated with the at least one print document. The ticket includes at least one tab attribute generated as a function of the received tab data. The job submission component submits a job to a printer and the job includes the ticket and the at least one print document.

Abstract: Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

Abstract: A method receives a print job and analyzes the complexity of the print job to generate complexity factors. The method performs raster image processing (RIP) on the print job and records the time taken to perform the raster image processing of each page of the print job. This generates “RIP times.” In addition, the method records the size of each page of the print job to generate “page sizes.” Then the method prints the print job and records the time it took to process the print job. Then the method determines how each of the complexity factors, the RIP times, and the page sizes contributed to the time it took to process the print job. This generates “complexity factor time values.” The method prints a report of the complexity factor time values detailing how each of the complexity factors contributed to the time it took to process the print job.

Abstract: A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.

Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.

Abstract: Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced.

Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.

Abstract: Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

Abstract: The invention disclosed here is a method for achieving simultaneous consideration of multiple customer demand dates within an advanced planning system. The invention provides a method of production planning that considers multiple due dates. The invention solves a production planning model based upon the second (commit) date to produce a first solution, sorts the demand records in order of importance, and then re-solves the production planning model based upon the first (request) date to produce a second solution. The re-solving process is performed on each demand item in the sorted order of importance. The invention optimizes between the first solution and the second solution. Before re-solving the production planning model, the invention changes the lower bound constraints on backorder variables. The re-solving process changes the required date for a single demand item, and this re-solving process is repeated for all demand items that have a first (request) date that is before a corresponding required date.

Abstract: Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

Abstract: The invention describes a method and system for conducting online marketing research keeping in consideration the specified budget for the experiment. The invention describes a methodology for effective data collection and optimised utilization of budget through the use of efficient sampling and grouping of users.

Abstract: A system and method for characterizing color separation misregistration of a multi-color printing system utilizing a broadband multi-channel scanning module, such as an RGB scanner, are provided. The system and method include generating a spectral reflectance data structure corresponding to a broadband multi-channel scanning module. The spectral reflectance data structure includes at least one parameter. The at least one parameter may correspond to the broadband multi-channel scanning module and/or a printing module. The system and method further provide for calibrating a spectral-based analysis module by utilizing the spectral reflectance data structure. The system and method also include characterizing color separation misregistration utilizing the calibrated spectral-based analysis module by examining at least one plurality-separation patch.

Abstract: The embodiments of the invention provide a method of organizing assets having artifacts in a repository. The method begins by organizing artifacts of at least one of the assets as internal nodes in a graph based on a context. The method simultaneously organizes the assets as external nodes in the graph based on the context. The internal nodes comprise artifacts having metadata that is updated by an artifact producer and/or an asset producer. Moreover, the external nodes comprise artifacts that are defined and/or updated by roles other than an artifact producer and/or an asset producer.

Abstract: Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on a bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., a single-fin or multi-fin MUGFET or multiple series-connected single-fin or multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections).

Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

Abstract: Embodiments herein include a method of combining a graphic image with other data to be printed, such as text or other graphics. One embodiment receives image data and document data and applies a mask to the image data to produce an image snippet. The mask adjusts a transparency of the image data in the image snippet by eliminating pixels from the image data. The method combines the document data and the image snippet into a page description language (PDL) file (PostScript file) using a print driver. One feature of the embodiments herein is that the image snippet is combined with the document data only by the print driver, and the image does not need to be combined downstream using an interpreter. After creating the PDL file, then the method processes the page description language file through an interpreter to produce raster data and prints the raster data on a media sheet using a printer.

Abstract: Disclosed are embodiments of a modular printing system with one or more modules having one or more bypass paths and comprise a modular printing system with a module (e.g., a stacker or feeder module) having a main compartment and at least one additional compartment. Contained within the main compartment is a main sheet transport path and a functional component (e.g., a sheet stacking device or a sheet feeding device) connected to the main sheet transport path. Contained with the additional compartment is a bypass path. The bypass path allows sheets to be routed through the module in the event of a print media sheet jam in the main sheet transport path. Because the bypass path is contained within a separate compartment, the jam can be cleared from the main compartment without cycling down the printing system, thereby allowing for continued productivity.

Abstract: A method is provided for quantitatively evaluating fiber tear associated with removal of a cover that was adhered to a spine of bound pages of at least one book. The method includes optically imaging the spine of each book from which the cover was removed and generating a corresponding at least one digital image, and processing the images using a tangible processor executing image processing software. The processing includes selecting regions of the images that have a color which corresponds to a range of colors associated with a selected level of fiber tear, assigning a selected color to the selected regions which is contrasting relative to the colors of non-selected regions of the at least one image, selecting at least a portion of the images to analyze, and determining a percentage of the selected portion that is assigned the selected color.

Abstract: A method and apparatus transfer a material from first roller within a container to at least one second roller, and transfer the material from the second roller to at least one third roller. The second roller and the third roller form a loading nip at a location where the second roller is closest to the third roller. The method and apparatus transfer the material from the third roller to at least one recipient device, and measure current flow between the second roller and the third roller using a measurement device. Then, the method alters the relative rotation rate difference between the first roller and the second roller based on the current flow to maintain a predetermined density of the material at the loading nip using a controller.

Abstract: Disclosed are embodiments of a color management system and an associated method that display a visual representation of a digital version of a document and further annotate selected object(s) in the visual representation with corresponding statement(s) containing a natural language description of any color differences between the selected object and the same object in a different digital version of the same document. For example, a visual representation of the print-preview version of a document can be displayed and a selected object within the visual representation can be annotated with a statement containing a natural language description of any color differences between the selected object and the same object in the selected-for-print-preview version of the document. By annotating selected object(s) on the display in this manner, the embodiments provide an accurate indication of color variations between the two versions even in a non-calibrated and/or non-optimal viewing environment.