Abstract: A clock error detection system is provided for a data processing system that employs multiphase clock signals and dual, substantially identical electronic modules. The clock error detection system employs one clock error detection circuit on one module and a second clock error detection circuit on the other electronic module. An error collector is coupled to the first and second clock error detection circuits on both modules to receive the fault signals. Two complementary residue code generators with different moduli are used in each electronic module to generate clock phase error detection signals, which may be used to detect either missing or extra clock phases.

Abstract: An optical waveguide is comprised of an optical fiber having a core and a cladding wherein the core comprises an organic polymer media exhibiting non-linear optical response over a predetermined optically transmissive region, the polymer having a predetermined index of refraction and the fiber having a predetermined uniform diameter and an arbitrary length. The fiber inherently possesses waveguide properties which are utilized for the detection of radio frequency fields, modulating optical signals, frequency doubling, and as a parametric amplifier.

Abstract: An instruction processor for a data processing system runs arithmetic sequences that are initiated by sequence designator signals and are interrupted by interrupt signals. During operation of the processor logic elements of the processor are selectively cleared by clear signals during time periods that sequence designator signals are in inactive states following the occurrence of an interrupt signal. Dual indentical logic circuits are employed wherein each of the circuits include error circuit elements that are coupled to receive the interrupt signal and arithmetic sequence initiation signals. A comparator is coupled to an output of each of the dual identical logic circuit to receive signals that are used to indicate when an interrupt signal and an arithmetic sequence initiation signal occurs simultaneously in only one of the logic circuits. Clear sequence circuitry in each of the dual identical logic circuits receives the interrupt signal and selectively supplies clear signals to the logic elements.

Abstract: An electro-optical light deflector utilizing layers of a non-linear electro-optically (NLO) responsive polymer for directing an exiting light beam in a given direction. Sandwiched between each NLO layer of a multi-layer array is a thin film electrically conductive layer that is connected to a voltage source. By applying an electric field across an NLO layer, a change in refractive index is induced and the phase of that portion of the optical beam passing through it is either retarded or advanced. Each layer in the NLO array sees a slightly different electric field and therefore produces a slightly different phase change in the portion of the propogating optical beam. This results in directing the reconstructed beam in a different direction. By applying different voltages to the electrodes, both beam shaping and changing beam direction are possible.

Abstract: A Record Lock Processor is utilized in a multi-host data processing system to control the locking of Objects upon request of each of the multiple host data processors in non-conflicting manner. The Record Lock Processor has storage provisions which include a Lock List for storing bits that identify the Objects and bits that identify the requesting processor, a Queue List that stores entries that are formatted like the Lock List entry when a prior Lock List entry has been made for the same Object, and a Cache List for each processor that stores Cache List entries that identify each Object that is stored in the cache memories, each of which Cache List entries is associated with one of the requesting processors, wherein such Cache List entries include validity bits that identify whether each Object stored in a Cache List has a Valid or an Invalid status.

Abstract: A novel memory access system is provided for simultaneously processing request for access to a plurality of memory banks. A plurality of input-output ports are coupled to a read bus and to a write bus which are in turn coupled to the memory banks to be accessed by read and write commands initiated by processors coupled to the I/O ports. Pipeline control means receive the request for access functions from the processors and are operable to resolve conflict between plural request. The pipeline control means sequentially raise either write or read request on control and address buses and generate time slot windows during which subsequent write or read data transfer operations will occur so that data being pipelined on the write and read buses is being simultaneously accessed.

Abstract: A single-ended DC-to-DC power converter which is operative at very high switching frequencies with zero-voltage resonant transition switching. A single magnetic element functions as both a storage inductor and a transformer. A charging capacitor is switched to induce a reversal current through the inductor for providing the zero-voltage switching function. Control to output characteristics are identical to those of conventional buck and buck-boost converters. The invention provides efficient, high-frequency operation and isolation of the output from the input power source with minimal component volume. The control system is adaptable to constant frequency pulse width modulation for voltage regulation.

Abstract: A novel partitioned parity check and regeneration circuit is provided for receiving an input data word which is partitioned and the partitioned bits are stored in a partitioning register to provide a subset input data word of fewer data bits than the input data word. Parity register means including a parity register are associated with the partitioning register to provide a parity check of the partitioned data word and for generating an error detect signal when the data bits in the partitioning register are not properly latched. The parity bits stored in the associated parity register are employed with associated output logic to generate regenerated parity bits associated with the output of the data bits in the partitioning register to preserve the integrity of the data.

Abstract: A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.

Abstract: A Fabry-Perot etalon is utilized as an optical switch for controllably switching an input optical signal on an input optical conduit between first and second output optical conduits. The etalon is comprised of a cavity formed by plane parallel periodic multilayer reflective surfaces with a variable index of refraction semiconductor medium sandwiched therebetween. The medium and periodic multilayer structures comprise, for example, Aluminum Gallium Arsenide. An optical pump injects an optical control beam into the medium to vary the index of refraction of the medium so as to cause the input optical signal to either be reflected from the cavity into the first output conduit or transmitted through the cavity to the second output conduit. Alternatively, electric fields, thermal fields, or injected carriers can be applied to the medium to vary the index of refraction thereof, thereby effecting the optical switching action.

Abstract: A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.

Abstract: A light emitting diode circuit with an emitter coupled logic (ECL) interface is provided with temperature compensation by a series circuit consisting of a pair of resistors which are separated by at least one diode. A first switching field-effect-transistor which receives the output of the interface has its drain-to-source path coupled to the junction of one of the resistors and the diodes, while an output drive field-effect-transistor has its gate coupled to the junction of the other resistor and the diodes and its drain-to-source path coupled in series with a light emitting diode (LED).

Abstract: A DC-to-DC power converter topology utilizing parallel connected transformers in a buck switching configuration with each stage operated 180.degree. out-of-phase, with the primary windings of the transformers sequentially feeding into a common filter capacitor. On each transformer, a secondary winding is switched to a load at the time the primary winding is shunted across the filter capacitor. The circuit provides dual inductor buck power stage operation while maintaining input-output isolation. Interleaved power processing provides continuous capacitance support for the output voltage produced by the power supply.

Abstract: An apparatus for moving a module in a guide channel includes levers which cooperate with cams associated therewith and contacting edges extending from the guide channels to apply forces for positioning the module. These forces are coupled to movable wedges, guided by wedges fixed to the module, which contact the walls of the guiding channels to clamp the module. Clamping forces are maintained by compressible elements such as Belleville washers or suitable springs coupled to the wedges fixed on the module.

Abstract: Bus error injection circuit generates bus errors to test proper operation of bus error detection and recovery in a system of modules interconnected by a synchronous digital bus. Application of the circuit is bus error detection and recovery tests for a physical realization of the system. The bus error injection circuit can be replicated on a number of modules interconnected by a synchronous bus to provide multiple sources of error injection. One module, or multiple modules, with error injection circuitry is designated as the source(s) to inject a transient bus error. The bus error injection circuitry monitors the bus to determine when the module is a participant in a bus transfer cycle on the bus. An error injection counter decrements for each such cycle. When the counter output value is one, the module derives its error injection pattern onto bus signal lines in place of the signal line values normally generated.

Abstract: Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.

Abstract: An optical switch for coupling one of a plurality of input light sources to one of a plurality of output terminals is comprised of a Bragg cell array acoustically excited in accordance with one or more preselected control frequencies from a selectable source of such frequencies. The beam deflection is proportional to the applied radio frequency. A scan lens is positioned to intercept the deflected beams and to focus the beams into a plane for imaging upon a linear array of optical output fibers. By choice of the control frequency any combination of input and output fiber optic lines may be optically coupled without requiring active sensors. Sufficient diffraction is provided by the Bragg cell in combination with the scan lens to minimize cross-talk and insertion loss.

Abstract: A memory system which is shared by a plurality of requestors each of which supply read and write address bits to the memory system is read out of, or written into, in accordance with read and write address bits. A sequencer is utilized to initiate a sequence of timing signals that control the reading, writing and partial writing of data. Certain ones of these signals occur at fixed intervals from the receipt of an initial load address signal. A read address circuit coupled to receive the read address bits generates a set of check bits. A read address stack means stores each set of read address check bits upon the occurrence of an associated load read address stack signal. A write address check bit generator means is coupled to receive write address bits and to generate a set of check bits representative of the write address bits. A write address stack means stores each set of the write address check bits upon the occurrence of an associated load write address stack signal.

Abstract: Apparatus for checking and detecting erroneous start signals is provided in the arithmetic section of a high speed instruction processor and may be embodied in other types of processors. The novel logic circuits include circuits for detecting an attempted start signal while a previous instruction is still in process; logic circuits for detecting when an even arithmetic sequence and an odd arithmetic sequence other than the first sequence are being concurrently processed; and logic circuits for detecting when an AR start instruction is being attempted during a wrong minor cycle.

Abstract: A log gauge for a chain saw is provided which enables an operator to repeatedly cut approximately equal lengths of firewood logs with only a minimal amount of effort being required to visually measure the logs. This accomplished by a mirror that is affixed to one leg of a frame member while the other leg is secured to the handle of the chain saw. The mirror is adjusted by an adjusting bolt so the operator can align on a visual indicator relative to the image of the end of the log in the mirror with respect to a scribed line on the mirror. One embodiment of the frame is formed by utilizing a unitary flexible plastic frame with a C-shaped bridge having a reduced cross sectional area that allows one leg to flex relative to the other thereby allowing the operator to adjust the mirror for different lengths of logs.