Abstract: In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.

Abstract: An optical bypass switch receives arbitrarily polarized light from an input optical fiber which is divided into the P and S-polarized light beams by a polarization beamsplitter. These P and S-polarized light beams are focussed to a magneto-optic garnet wherein the plane of polarization is rotated in accordance with a desired switching function and directed to an output optical fiber determined by the polarization rotation state established in the magneto-optic garnet.

Abstract: An electroplating rack is constructed of corrosion resistant stainless steel, with oppposed side frames milled with vertical channels to accommodate opposite side edge portions of a printed circuit board for plating. Mechanical and electrical connections with the circuit board are made with recessed stainless steel screws with rounded tips. Current is provided to the top of the rack, and also to the bottom of each side frame through an elongate, vertically disposed copper bar surrounded by an insulative sheath and contained within each side frame. Each of the copper rods is threadedly engaged in a steel end cap at the bottom of the associated frame. The current fed into the top and bottom of the rack can be adjusted by adjusting the comparative conductivity of the two paths.

Abstract: Conceptual structures which can be used to represent any knowledge that can be represented by frames/units. Its realization, in a software program called Unit Interface, provides a method of storing frame/unit data in conceptual structures and algorithms for accessing that data when stored in conceptual structures as if it were a frame/unit or collection of them.

Abstract: A laminated printed wiring board having surfaces thereof fabricated from conventional fiber reinforced laminates which are secured together by means of an adhesive fabricated of a reinforced thermosetting resin having a coefficient of thermal expansion (CTE) which is substantially smaller than the CTE of the surface laminate whereby the apparent CTE of the overall printed wiring board assembly is substantially controlled.

Abstract: A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.

Abstract: Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Abstract: A full bridge switching power converter employs zero-voltage, resonant-transition (ZVRT) switching techniques which appreciably reduces the switching losses at high switching frequencies, (for example, 1 MHz and above), using constant frequency, pulse-width-modulation techniques. The converter is implemented using a transfer with four switching FET's coupled to the primary of the transformer and four switching FET's coupled to the output of the transformer and a control unit that supplies the constant waveforms necessary to achieve synchronization and timing required to achieve the ZVRT switching.

Abstract: The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

Abstract: A high-speed partitioned set associative cache memory is provided with a plurality of cache memory boards. Each of the boards is provided with a partial data array and a full tag array on each board. At least one memory address register is mounted on each of the boards with the partial data array and the full tag array for receiving a unique address from the central processing unit which enables the plurality of memory address registers to simultaneously access addresses in the partial data arrays on different boards and to also address tag addresses associated with the data addresses by sequencing controls mounted on a separate board with logic circuits which monitor output signals from the data arrays and the tag arrays. The output signals resulting from accessing memory locations in the cache memory are coupled to logic circuits for determining the type of error and the exact array where a single error has occurred.

Abstract: Failures of duplicate input signals to two indentical electronic modules which may be units, cards, circuits or other entity, are detected by comparison. In each electronic module functional input signals are captured in a plurality of latches on different, or the same, clock phase. Each input signal is captured directly in latches on the same phase as the functional latch which used it to provide a plurality of link signals which are encoded by techniques, such as parity or residue encoding, and compared. The result of the link signal comparison is stored in a register. The outputs of the register are encoded and are supplied to a comparator which compares a signal from the other identical electronic modules. When miscomparison occurs location of the type of failue is facilitated by the system.

Abstract: A variable refractive index device, such as a Bragg cell, is temperature stabilized by sensing ray path deviations of a secondary diffracted beam. Two photodetectors with centers offset from the exit position of the central ray of the beam at normal temperature operation receive light energy as a function of the deviation of this ray path from the normal position. Light in each fiber is detected to derive electrical signals that are utilized to establish a correction signal to a voltage controlled oscillator which varies the frequency thereof and compensates for the diffraction deviations caused by temperature variations.

Abstract: A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory.

Abstract: A voltage regulator particularly adapted to A.C. distributed power systems requiring independent voltage regulation at a plurality of frequency responsive power supply modules energized by a power source at a common alternating frequency is provided by resonant tuning of the regulator circuit. An LC resonant circuit determines the operating frequency of the regulator, and may be operated above or below the excitation frequency. The output voltage is applied to a current amplifier which energizes a linearly variable inductor in accordance with the sensed D.C. output voltage. Changes in the output voltage result in changes in the tuned frequency of the LC circuit and the corresponding corrective change in the output voltage. Circuits providing both voltage and current regulation are described.

Abstract: A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

Abstract: An optical light conducting fiber that has a D-shaped stress sensitive coating of PVF.sub.2 which covers substantially equal length segments of said fiber, so that each of said segments is separated by equal uncoated segments of substantially the same length as said coated segments. The fiber when used in an interferometer provides an antenna that is capable of sensing electromagnetic and other stress-inducting waves in the environment. The optical fiber is polarized by winding it on a specially designed spool, heating it and applying a high intensity electric field in the desired direction.

Abstract: An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.

Abstract: A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.

Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.