Abstract: A system for detecting and isolating fault conditions occurring within a digital electronic system. The digital electronic system includes a first digital logic array for generating digital outputs in response to a set of digital signal inputs applied to it. The digital logic array is replicated and the second array is configured to receive the same inputs as the first. The first and second arrays are made to operate in synchrony so as to normally produce identical outputs in the absence of fault conditions occurring either in the first or second array or in the inputs applied to them. The digital outputs from the first array are applied to first and second residue code generators having different modulii. Likewise, the outputs from the second arry are applied to third and fourth residue code generators which are identical in make-up to the first and second residue code generators.

Abstract: A regulator circuit for equalizing the load currents of a plurality of power supply modules connected in common to feed a common load. Each of the modules includes a pulse-width modulator for adjusting the duty cycle of the module, thereby to adjust the voltage regulation point and corresponding current output of the module. A current sensor produces a current level signal proportional to the current output of the module. The current level signal is applied through a current amplifier to generate a corresponding variable error voltage. A fixed reference voltage derived from the output voltage and the variable error voltage are applied to the pulse-width modulator to vary the duty cycle so as to produce a decrease in load voltage with an increase in current output and an increase in the load voltage with a decrease in current output thereby equalizing the current output of the module with modules having substantially equal output voltages.

Abstract: A multibank computer memory system is provided in which the storage banks monitor the initiate line while each bank operation is being processed to verify that another initiate is not received before it can be processed. This serves to check that the control logic is not in error, and that there is no error between the control section and the banks.

Abstract: A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A Start Bit Code defines the location of the start of the bit field to be written and an End Bit Code defines the bit after the last bit that is to be merged and written. Write and Read Data to be used in the partial merge operation are stored in a Merge Register along with a code derived from the Start and End Code bits. The bits not used are stored in a Non-Merge Register. Parities are compared to verify that a parity error did not occur when the Merge Register was loaded.

Abstract: An improved interface arrangement between an antenna controller and one or more antennas. The interface includes a reduced number of control lines but is capable of handling complete interface requirements including control and status between the antenna controller and the antenna.

Abstract: A Surface Wave Acoustic (SAW) is constructed with hyperbolically curved electrode fingers. The transducers consist of relatively narrower inner electrode fingers and relatively wider outer electrode fingers, and may also be divided into a plurality of tracks with each of the tracks being subdivided into a plurality of subtransducer elements which are capacitively coupled in electrical series.

Abstract: Manchester level coded data is converted to NRZ by two gated delay line oscillators responsive to differential Manchester signals for providing a single gated pulse in response to consecutive data cells conveying the same data and for providing two pulses in response to a data change. A decoder circuit responds to the two pulse condition by toggling a data flip-flop that provides the NRZ data. The flip-flop also controls gates responsive to the two oscillators for selecting between the two oscillator signals to provide the NRZ clock. When the system bus ceases data transmission, three or more oscillator pulses are generated, the detection of which is utilized to preset the data flip-flop.

Abstract: An optical bypass switch includes a variable diffraction element responsive to acoustical signals operable to couple light signals incident to first and second input ports to first and second output ports, respectively, for a first diffraction index and from the first and second input ports to the second and first output ports, respectively, for a second diffraction index. Acoustical signals are provided by an electro-acoustic transducer coupled to the variable diffraction element which establishes acoustical signals in response to acoustical signals coupled thereto.

Abstract: A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines of a pair, and a base coupled through a diode means to the second bit line. A second bipolar transistor has its collector-emitter path coupled to the second bit line and its base coupled through a second diode to the first bit line. The collectors of both of the bipolar transistors are coupled to provide an output signal. Resistors are coupled to a pulse source and to both of the bases of the bipolar transistors. A current sink is coupled to both of the select bit lines. The diode means are connected so as to be forward biased when the base-emitter junction of the transistor to which the diode means is coupled is also forward biased.

Abstract: An optical waveguide for transmitting light energy is defined by a glass capillary with a core of noncentrosymmetric non-linear optical polymer which has been poled to induce a stable axial alignment of molecules therein. Changes in refractive index of the polymer are induced by an applied electric field. In a preferred embodiment, the waveguide is used as an electric field sensor and may form an arm of a Mach-Zender interferometer. The device is adapted to modulate waveguided electromagnetic energy by a change in refractive index proportional to the applied electric field. In a further embodiment, the birefringent properties of the polymer are used to cause polarized light energy transmitted by the waveguide to undergo a change in polarization, which, when intercepted by a polarization sensitive analyzer, provides an amplitude modulation of the transmitted light energy.

Abstract: A single stage power conditioner which produces an isolated DC output while drawing resistive input current from the utility has been described. A high frequency switch-mode technique was used which operates in continuous conduction mode to reduce electro-magnetic interference (EMI) generation and ripple losses.

Abstract: A left justification scale factor generator is described which is capable of scaling numbers for binary number groups off one, two, three and four bit groups. Two basic building block circuits are utilized in the scale factor generator's priority encoder, which looks at four binary bits and produces a two bit binary count that corresponds to the first non-zero input found, and an algebraic priority encoder which also receives a reference signal that allows it to indicate the significance of the priority detection level. By sensing correction factors at the first level of the system, the number of logic levels are kept to a minimum.

Abstract: A full bridge DC-DC series-resonant power converter is operated at a constant switching frequency using a phase delay between the transistor legs of the bridge to control the output voltage. All power semiconductor devices switch on and switch off at approximately zero volts while operating at a constant switching frequency which is above the resonant frequency of the resonant tank circuit. Zero-voltage switching increases the efficiency of the power converter and allows high frequency operation which minimizes component volumes. Constant frequency operation simplifies design of the magnetic components, confines the EMI spectrum to known frequencies and simplifies EMI design, and reduces the voltage and current excursions and thus reduces the peak component stress.

Abstract: A surface acoustic wave (SAW) radar doppler shift detection system is provided by transmitting a modulation signal having an up-chirp component followed by a downchirp component from a dispersive array SAW assembly to a target, and then receiving the radar return from the target by a receiver which also employs a similar dispersive array assembly. Dispersive array assemblies are constructed with two in line dispersive arrays. The dispersive arrays of the transmitter is positioned relative to two input SAW transducers and two output SAW transducers such that a pulse signal supplied to the two input transducers results in an expanded signal of the output transducers. The expanded signal acts as a modulation signal which is multiplied by an RF and transmitted. The receiving array assembly detects the radar return signal, and, after it is multiplied down to the SAW frequency, compresses it.

Abstract: A fiber-optic switchboard is developed consisting of a plurality of n input fibers, n input lenses, n light deflecting elements, n relay lenses, a multifaceted reflector, m output lenses, and m output fibers. Each input lens causes an image of the end of the corresponding input fiber to fall on its deflecting element, while each relay lens causes an image of the corresponding deflector element to fall on the proper facet of the multifaceted reflector. Each output lens causes an image of the multifaceted reflector to fall on the face of the corresponding output fiber. The output lenses are placed such that each deflecting element is capable of directing light through any output lens and into the corresponding output fiber.

Abstract: A Layered Network system may provide varying cost from order NlogN low-cost networds, to completely-routing, fully-Layered networks with cots of order Nlog .sup.3 N. Layered networks are composed of switches and point-to-point connections between them. These networks establish connections from requestors to responders by relaying "requests" through the switches. Each switch has built-in control logic to route requests and responses. The switch setting is determined using the comparison of the request with the request's current location in the network, and with locally competing requests. To provide distributed routing without a centralized controller, each switch routes the requests using only the information contained in the requests that switch handles. The switch setting is remembered in order to route the responses on the same paths as the associated requests, but in the reverse direction.

Abstract: An apparatus for maintaining an arbitrary orientation of the polarization of an antenna, such as an airborne microwave antenna, by using antenna pointing information and platform (aircraft) attitude information to position the input/feed signal.

Abstract: A pulse width modulation control circuit utilizes a retriggerable monostable multivibrator as a high speed comparator which compares a reference waveform with a control signal level to effect variable termination of modulated output pulses. The control circuit finds particular applicability to pulse width modulated switched mode power supplies.

Abstract: A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

Abstract: A connector having a housing with a number of cavities that receive connector pins is conformally coated. A thixotropic, curable material is used to seal-off the cavities at the end where the contact tails for the connector pins emerge from the housing. The sealing material seals off the cavities from the environment but does not extend so far into the cavities that electrically insulates the connector portion of the connector pins. The sealing material is preferably both ultravioletly-curable for rapid curing and heat-curable to cure the material in shadow areas.