Abstract: A method and device for adapting a signal is provided. The signal includes a number of recurring samples of data. In one example embodiment, the method receives recurring samples of data. Each of the samples of data includes a first number of elements. A second number of elements are selected from at least one of the recurring samples. The second number of elements is approximately less than the first number of elements. The selected second number of elements are substituted with respective phase altered elements. The subject matter also provides a method and device for identifying a signal property(ies) and a computer system for implementing these methods.

Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.

Abstract: A system and circuit for virtual power grid is disclosed. In one embodiment, a switch system for a virtual power grid includes a first transistor for connecting a power supply to a node of a virtual power grid for an isolated region of circuitry via the first transistor upon a receipt of a first control signal to turn on the first transistor. The switch system further includes a second transistor for connecting the power supply to the isolated region of circuitry via the second transistor upon a receipt of a second control signal to turn on the second transistor. In addition, the switch system includes a self-timed enable module for generating and forwarding the second control signal when a voltage level at the node of the virtual power grid which is charged by the power supply via the first transistor reaches a threshold voltage.

Abstract: Hierarchical storage management (HSM) for redundant array of independent disks (RAID) which comprise a plurality of drive trays of different types is disclosed. In one embodiment, a method for hierarchically managing RAID which includes a plurality of drive trays of different types, includes writing data to a tray of a first type, periodically monitoring a use of the data, and moving the data to a tray of a second type if the use of the data yields less than a threshold value. Each one of the tray of the first type and the tray of the second type includes at least one hard drive, and a composite score of price, capacity, performance, and function of the tray of the first type which is higher than a corresponding composite score of the tray of the second type.

Abstract: A system and method for generating an orthogonal array (OA) for software testing is disclosed. In one embodiment, the method for generating an OA of test cases for testing a system includes accepting a user input from a user, the user input including multiple factors and multiple levels associated with the system, accessing a reference table to determine a set of parameters based on the user input for testing each level of a factor against all levels of all other factors in the system, and performing a predetermined number of iterations based on the set of parameters to generate the OA of the test cases. The OA of the test cases includes combinations of the multiple factors and the multiple levels required for testing pair-wise interactions between the multiple levels and the multiple factors in the system.

Abstract: A technique for improving image quality using dynamic gray scale correction, in one example embodiment, includes dynamically computing non-linear gamma curves using histogram data extracted from a current video frame. A gray scale correction is then dynamically applied to each pixel in the current or next video frame as a function of the computed non-linear gamma curves.

Abstract: A memory manager for a system, a system that includes the memory manager and a method of using thereof are provided. The memory manager manages memory allocations in at least a memory. The memory manger comprises, a first unit configured for receiving a plurality of requests from one or more components of one or more applications of a system. The memory manager also includes a second unit configured for optimizing memory allocations for the plurality of requests.

Abstract: A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth table including state information associated with input pins and their associated output pins in the digital circuit. Valid arcs are then determined based on whether a change in each of the input pins causes a change in associated one of the output pins using the received truth table. A first arc table is then formed using state information associated with substantially the determined valid arcs. Redundant arcs are then identified in the first arc table using the associated state information. A second arc table is then formed by removing the state information associated with the redundant arcs from the first arc table.

Abstract: A system and application design model deploys self-describing modules (e.g., COTS-component off the shelf) of code or services that can be reused on-demand and composed into multiple processes and composite solutions. Also described herein is a method of providing a modular prescriptive architecture for a user of a business process to obtain reusable services which are composed into service oriented multiple processes and composite solutions on a web-application. The prescriptive architecture is SOA oriented and uses a plurality of tiers including a client tier, a presentation tier, a business logic tier, an integration tier, and a data tier, as well as an infrastructure service layer designed across and interacting with the plurality of tiers. Each tier may have further layers. The prescriptive architecture provides data integrity, is scalable, flexible, and extensible, and can be internationalized. A method of designing a software prescriptive architecture is also included.

Abstract: A method and system for processing geometrical layout design data in a computation network. The method includes assigning one or more partitions of the geometrical layout design data to one or more computing devices. One or more partitions are assigned based on first predefined parameters. The method further includes receiving a minimum-hierarchy representation of the geometrical layout design data and a partition information corresponding to one or more partition assigned. The partition information corresponding to a partition assigned includes a spatial information corresponding to the partition. Further, the minimum-hierarchy representation includes a plurality of cells. Each cell in the minimum-hierarchy representation may include zero or more bounding box information and zero or more cell-references. Further, the method includes retrieving one or more fragments based on each of the partition information and the minimum-hierarchy representation.

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract: A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geometrical layout design data extracted from one or more data-format files into each of a structural data, a spatial data, and a raw-geometry data. Thereafter, one or more predefined operations are performed on one or more of the structural data, the spatial data, and the raw-geometry data.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A technique for computing perceptual noise in an audio signal that is computationally efficient. In one example embodiment, the technique includes computing perceptual noise in an input audio signal. The steps involve pre-computing NER (noise-to-excitation ratio) values associated with critical bands within a frame by zeroing out associated spectral coefficient values before the quantization loop, and also assuming bands with lower spectral energy than the band under consideration are zeroed out during quantization. When a critical band is zeroed out during quantization, the associated NER values which have been pre-computed are used in computing an overall perceptual distortion of the frame.

Abstract: A method and system of a software development using visual action elements is disclosed. In one embodiment, the method includes providing a user interface with action elements, and providing a mechanism for specification and review of the action elements using the user interface. For example, providing a user interface includes providing a prototype of the user interface in a web browser and providing a mechanism for specification and review includes providing a toolbar with functionality to record user comments regarding the action elements. The method may also include providing a user interface to document the user interface. The method may further include providing an animated view of stimulus response behavior of the action elements.

Abstract: A novel technique for combining deinterleaving operation with Fast Fourier Transformer (FFT) modules and other post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.

Abstract: A motion estimation algorithm finds the best match for a given block or macroblock so that the resulting error signal has very low energy level which is computed, for e.g., by the SAD method. The motion estimation algorithm also provides for an optional sub-pixel level estimation and an inter4v search, and allows for restricting the number of searches for a Frame-frame ME (motion estimation) using Top-Top and Bottom-Bottom field MEs. The algorithm provides for a selective early exit and enables selecting a suitable search area with N candidate points (4 to 8) for starting the search. The search is conducted progressively till a minimum error signal (low energy level signal) is reached. The candidate points for search may be in a diamond shaped configuration, and there may be a plurality of successive diamond configurations, the number of which is configurable. The invention has application in MPEG-4 and H.264 standards.

Abstract: A synchronizer and a method for synchronizing a communication signal are presented. The synchronizer comprises a first unit arranged for receiving a plurality of inputs. The plurality of inputs include at least an indicative of a source clock period of a source clock domain, an indicative of destination clock period of a destination clock domain and a communication signal. The first unit being configured for stretching the communication signal according to the indicative of the destination clock period and indicative of the source clock period. The synchronizer is further provided with a second unit. The second unit is configured for operating according to the indicative of destination clock period. The output of the first unit is provided to the second unit. The second unit is configured for providing a synchronizer output signal corresponding to the communication signal operable in the destination clock domain.

Abstract: A technique for improving the performance of OFDM (Orthogonal Frequency Division Multiplexing) systems addresses the Sampling Frequency Offset (SFO) estimation and correction problems of conventional techniques and provides improved performance in a wide range of operating conditions. The technique teaches a correction scheme that uses known pilots in each OFDM symbol to estimate slope of phase error and subsequently calculate the correction factor for each of the sub-carriers in the associated OFDM symbol. The present subject matter further teaches an averaging slope estimates over a window of predetermined number of OFDM symbols to average out noise and get a refined correction factor. In addition, the present technique teaches tracking rate of growth of slope across OFDM symbols to estimate SFO, which can be used for the timing error correction in the time domain.

Abstract: A method and system for a product line management is presented. The system is capable of performing steps of the method. The method includes a first step of obtaining a product line architecture (PLA). A second step of obtaining a Change Management Workflow (CMW), the CMW includes a plurality of change activities, and the CMW being capable of interacting with the PLA. A third step of obtaining value stream maps for both the PLA and the CMW. A fourth step of creating activity lines for each of the change activity according to the PLA and the CMW. A fifth step of computing risk indicatives for the PLA and the CMW. A sixth step of triggering changes in the PLA and the CMW according the change activity, activity line, risk indicatives, or any combination thereof. And another step of repeating the steps of obtaining value stream maps onwards while managing the product line.