Abstract: Apparatus and method for generating first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz respectively, for use in a wireless transmission system deploy only first and second PLLs which are configured to generate 6336 MHz and 2640 MHz signals respectively with only in-phase components. Frequency dividers are employed for frequency-dividing the 6336 MHz signal severally by 2, 4, and 12 to obtain frequency-divided intermediate outputs with both in-phase and quadrature components. The intermediate output components and other intermediate signal components are selectively combined in a mixer (e.g., a single side-band mixer), for deriving the first, second and third carrier frequencies of 3432 MHz, 3960 MHz and 4488 MHz with both in-phase and quadrature components. The invention has application in UWB, WPAN, WLAN, or other wireless systems and has the simplicity and advantages of using only two PLLs instead of the prior art arrangements of three PLLs.

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract: A system for transmitting data in wireless communication employing an improved orthogonal frequency division multiplexing (OFDM) transmitter is devised. The orthogonal frequency division multiplexing (OFDM) transmitter is improved for VLSI implementation. The improved orthogonal frequency division multiplexing transmitter is configured to provide multi-rate support, low latency, reduction in the turnaround time and reduction in the gate count during data transmission.

Abstract: A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is accomplished by detecting data bits in an unsynchronized digital data stream by finding start of each data bit based on an estimated data bit width and transitions in the unsynchronized digital data stream.

Abstract: A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 22n?2 LSB (least significant bit) voltage levels are generated as outputs from 2n cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n?2) bits and (2n?1) bit resolution with lower SNDR are achieved by using 2n resistors and two current sources. In one described embodiment, 2n unit impedances in the cyclic string result in 2(n?1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.

Abstract: A group metering method (and system) for monitoring electrical energy consumption by a plurality of proximate users replaces multiple individual user-meters by a single electronic meter. A single computational engine computes consumed energy values by the users and deploys a single subsection set (display, real time clock, and non-volatile memory) which can be located on a PCB. The system, usable for single or three phase, may be located out of reach from the users to make it tamper proof. Individual ADCs obtain electrical current values (through current transformers,) of power consumed by individual users and cooperate with a single DSP to compute energy consumption by individual users, readable on a common display in round robin fashion. Differences between the sum of energy values consumed by the users and a consolidated energy reading beyond a known threshold are reported as possible user-tampering. Asynchronous communication ports communicate with display units and AMR modules.

Abstract: A technique to provide a distortionless and predictable real-time PWM waveform based on a sequence of combinations of programmed period and width values received from a processor. In one example embodiment, this is accomplished by using two sets of registers to store the period and width values and a tertiary period register to further store the period value with their associated timing controls to provide the predictable real-time PWM waveform.

Abstract: A method of managing a processing system that has at least one processor, uses the steps of: measuring MCPS (million cycles per second) utilization in the at least one processor; estimating a cycle count requirement for an algorithm on least one processor based on measured MCPS utilization; and, estimating an ability to run multiple applications on the at least one processor by assessing MCPS requirements and estimated cycle count requirement. Measurement of the MCPS utilization is preferably done by using the steps of: choosing a critical path in the processor, e.g., by taking hard real time requirements into consideration; measuring time taken for processing along said critical path; and, calculating MCPS requirements along said critical path using the measured time taken and a current processor clock speed. The inventive method has application in 802.11 MAC. Also described is a programmed storage medium to execute the described method.

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Abstract: The proposed technique uses basic properties of a Huffman codebook to decode a coded data bit stream having a plurality of variable length codewords based on the Huffman codebook. This is achieved by sorting codewords in the Huffman codebook based on potential values. The potential values are computed using the basic parameters of the codewords in the Huffman codebook. A current bit sequence having a predetermined length is extracted from the coded data bit stream. A potential value of the extracted bit sequence is then computed using the basic parameters of the codewords in the Huffman codebook. The sorted Huffman codebook is then searched to find a computed potential value in the sorted Huffman codebook that is substantially close to the computed potential value of the extracted bit sequence. The extracted current bit sequence is decoded based on the outcome of the search.

Abstract: A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.