Abstract: Manufacture of an integrated circuit flash memory devices includes covering a semiconductor substrate with a tunnel oxide layer, a floating gate layer, an intergate dielectric layer, a control gate layer, a silicon dioxide dielectric layer over a silicon nitride layer. Then those layers over the tunnel oxide are patterned into flash memory gate electrode by etching through a source/drain mask followed by ion implanting source/drain dopant ions through the openings formed by etching. Sidewall spacers are formed followed by a dielectric layer through which source line openings are etched down to the source/drain regions. Plug openings are made down to the source/drain regions. An intermetal dielectric layer is deposited comprising PEOX/SOG/PEOX over the device. Then via openings are made over the drain plugs by etching the intermetal dielectric layer through a via mask. Next metal is deposited over the intermetal dielectric layer into the via openings extending down into contact with the drain plugs.

Abstract: In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.

Abstract: A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.

Abstract: A flash memory EEPROM transistor is formed on a surface of a semiconductor substrate. In portions of the substrate, at the surface thereof, a doped source region and a doped drain region are formed with a channel region therebetween. A tunnel silicon oxide dielectric layer is formed over the semiconductor substrate aside from the source region. Above the source region is formed a gate oxide layer which is thicker than the tunnel oxide layer. Above a portion of the tunnel oxide dielectric layer, over the channel region and above a portion of the gate oxide layer is formed a stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer. The source region is located on one side of the stacked gate structure with one edge of the source region overlapping the gate structure. The drain region which is located on the other side of the stacked gate structure with one edge thereof overlapping the gate structure.

Abstract: A method of for manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a first polysilicon layer on the semiconductor substrate, patterning and etching the first polysilicon layer, formation of an interpolysilicon layer over the first polysilicon layer, patterning and etching an opening through the interpolysilicon layer exposing a contact area on the surface of the first polysilicon layer, forming a dielectric load resistor in the opening upon the contact area on the first polysilicon layer, and formation of a second polysilicon layer on the device over the dielectric load resistor, over the interpolysilicon layer.

Abstract: A manufacturing control system uses computer control of work flow for automatic production line control. The process is to sort (Work in Process) WIP by priority and queue time; select high priority WIP; and sort WIP by queue time and batch with other WIP by the same recipe. Calculate a dynamic dispatching ranking except for high priority batch WIP. Select the high priority stage and batch the high priority stage by recipe based upon queue time management. Test whether the line remains loaded at capacity. If the line is below capacity, interrupt the method. If the line operates at capacity, then branch to recalculate the ranking. Then return to select the high priority stage and select the batch high priority stage by recipe based upon queue time management.

Abstract: Testing probes in a testing apparatus are supported in a unitary structure to provide rigidity of the supports for the probes in testing. The spring probes have a contact head at the distal end from the probe tip with a set of antirotation tabs which lock in a cooperating antirotation slot in the probe guide. The contact head has a cone-shaped pilot at its tip which is engaged with a gold-plated contact spring. The inner diameter is integrally in contact with the pilot by mechanical engagement or bonding by soldering or laser welding or the like.

Abstract: A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

Abstract: An MOS electrostatic discharge, ESD, protection circuit for protecting semiconductors from ESD damage is formed on a doped silicon substrate. The circuit includes three stages. The first stage includes a first MOSFET transistor and a grounded region formed in the substrate. The first MOS transistor has a source/drain circuit connected between the first node and ground, and has a control gate electrode connected to ground. The second stage includes a string of MOSFET transistors connected in a series string. The transistors in the string are in sufficient number to provide a circuit which will conduct at a high current level to protect the output circuit from overvoltage when the voltage exceeds a critical value. The third stage includes a third stage MOSFET device with a control gate connected to the second stage output and to the output of the circuit. The source and drain circuit of the third stage device are connected between the third node and the ground connection.

Abstract: A substrate is covered with a gate oxide layer between FOX regions with a blanket lower lamina for a gate on the surface. A Mask code mask has a window overlying the desired gate location. A doped code implant region is formed in the substrate by ion implanting code implant dopant through the mask. Following mask removal a blanket upper lamina of the gate covers the lower lamina. A gate mask covers the upper and lower laminae. The gate mask is patterned to protect the gate region over the device, leaving the remainder of the upper and lower lamina exposed. Exposed surfaces of the laminae are etched away leaving a laminated gate. Lightly doped regions are formed in the substrate between the FOX regions and the gate by ion implanting dopant through portions of the gate oxide layer unprotected by the gate; forming spacers next to the gate; and forming source and drain regions in the substrate between the FOX regions and the spacers adjacent to the gate.

Abstract: An EPROM device is provided with self-aligned bit-lines. A tunnel oxide layer is formed on a semiconductor substrate. Blanket layers of doped, polysilicon layer, an interelectrode dielectric layer and a blanket polycide layer are formed over the dielectric layer. A TEOS dielectric layer is formed over the blanket polycide layer and a silicon nitride layer. A self-aligned source and drain etching process forms EPROM gate electrode stacks with trench spaces between the stacks in an array. Source/drain dopant ions are implanted in an MDD N+ process between the stacks forming alternating source and drain regions below the spaces between the sidewalls. Spacer dielectric structures are formed adjacent to the sidewalls over the drain regions leaving narrow drain spaces therebetween and spacer dielectric plugs completely filling the spaces over the source regions. An additional N+ implant is made between the spacers into the drain regions.

Abstract: Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl.sub.3 doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of C.sub.fp, capacitance of the P type capacitor and C.sub.fn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

Abstract: A DRAM capacitor is formed over a device with FOX regions and device areas with S/D regions. Form a planarization silicon oxide layer over the device and FOX areas covered with an etch stop layer and a first portion of a first capacitor plate over the planarization layer, a contact opening to the S/D areas by etching through the first capacitor layer and layers down to a S/D region. Form a second portion of a first plate over the device and through the contact opening into electrical and mechanical contact with one of the S/D areas, the second portion has exposed sidewalls and a top surface extending above the surface of the device. Form sacrificial spacers adjacent to the sidewalls of the second portion. Deposit a third portion of the first plate over the device. Etch back the third portion down to the etch stop layer to expose the sacrificial structure and remove the sacrificial structure. Form an interconductor dielectric layer and an upper capacitor plate extending between the second and third portions.

Abstract: This is a dynamic dispatching method for delivery performance by a factory. SLACK=(Due.sub.-- Date-Now)-(Forecast.sub.-- FAB.sub.-- Out.sub.-- Time); where Due.sub.-- Date=Scheduled due date from Master Production Schedule. The OTD (On Time Delivery) dynamic dispatching method focuses on the due date and the target cycle time under the environment of integrated circuit manufacturing. SLACK policy controls the long term due date and the OTD policy reflects the short term stage queue time. Through fuzzy theory, SLACK and OTD policies are combined as a dispatching controller to control the lot priority of the entire production line. The work piece, with either a long stage queue time, or with an urgent due date is pushed through the overall production line instead of jamming the front end of the process. A demand pull system satisfies the due date and the quantity of monthly demand.

Abstract: An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the same position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.

Abstract: This method provides for increasing integrated circuit production of a fabrication facility comprising collecting data from a plurality of machines, calculating of the present Ratio of Running Work (RRW), comparing present RRW to optimum RRW, checking the system to determine which machines are idle, and taking steps to increase the number of running machines. Steps taken to decrease the number of idle machines include dispatching commands to a computerized dispatching system or operators. The steps of the process are repeated to further increase RRW.

Abstract: A CMOS Mask ROM semiconductor device is formed in P-well NMOS region of a silicon semiconductor substrate with FOX regions on the surface thereof. A method of forming the device includes forming gate oxide over the substrate between FOX regions; forming a control gate layer over the gate oxide. Then form a gate mask over the device with and pattern a gate electrode and the gate oxide layer by etching through mask openings. Next, form an LDD mask over the device exposing the gate. Ion implant a P type dopant of a first dosage level through mask openings forming reverse type LDD implant doped P type regions. Form spacers adjacent to the electrode over the substrate. Ion implant an N type dopant of a second dosage level through the opening in the mask and aside from the spacers and the electrode into exposed portions of the substrate.

Abstract: A data processing system has display means with a display screen requiring a screen display instruction with each line of textual comments in a file to be displayed on the screen and means for associating comments to be presented on the display screen of a data processing machine with programming data in a sequential format, with means for designating the comments by a label placed before the commencement of the comments. Means are provided for interpreting the label to insert print display command indicia associated with the textual comments for printing the comments upon the display screen. The label is interpreted by means of an external program.

Abstract: Testing probes in a testing apparatus are supported in a unitary structure to provide rigidity of the supports for the probes in testing. The spring probes have a contact head at the distal end from the probe tip with a set of antirotation tabs which lock in a cooperating antirotation slot in the probe guide. The contact head has a cone-shaped pilot at its tip which is engaged with a gold-plated contact spring. The inner diameter is integrally in contact with the pilot by mechanical engagement or bonding by soldering or laser welding or the like.

Abstract: A metal oxide semiconductor field effect transistor with a lightly doped silicon substrate includes an oppositely doped well and oppositely doped source region and oppositely doped drain region with respect to the lightly doped substrate, the improvement comprising at least one counter doped region formed along the surface of the oppositely doped well between the source and drain regions. The substrate comprises a P-substrate, the well comprises an N- well and the counter doped region is doped P; the counterdoped region comprises an island among a plurality of islands between the source region and the drain region. The counterdoped region comprises an island among a plurality of islands between the source region and the drain region.