Abstract: An SRAM transistor cell on a doped semiconductor substrate comprises two access FET transistors and two storage FET transistors. A first load capacitor has a plate connected to a first node with the other plate connected to the power supply. A second load capacitor has a plate connected to the second node with the other plate connected to the power supply, a bit line and a bit line bar. The first storage transistor drain connects to the first node. The second storage transistor drain connects to the second node. The storage transistors have interconnected sources. The first node connects via a first interconnection line to the second transistor gate. The second node connects via a second interconnection line to the first transistor gate. First and second access transistor gates connect to a wordline. The first access transistor drain connects to the first node. The second access transistor drain connects to the second node. The first access transistor source connects to the bit line.

Abstract: In a semiconductor manufacturing fabrication plant with production to-order type operation, hundreds of devices and various processes are managed. To provide short cycle time and precise delivery to satisfy customer expectations is a major task. A dispatching algorithm named "Required Turn Rate (RTR)" functions according to the level of current wafers in process (WIP) algorithm revising the due date for every lot to satisfy the demand from Master Production Scheduling (MPS). Further the RTR algorithm calculates the RTR of each lot based on process flow to fulfill the delivery requirement. The RTR algorithm determines not only due date and production priority of each lot, but also provides RTR for local dispatching. The local dispatching systems of each working area dispatch the lots by using required turn rate to maximize output and machines utilization.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: Manufacture of an integrated circuit flash memory devices includes covering a semiconductor substrate with a tunnel oxide layer, a floating gate layer, an intergate dielectric layer, a control gate layer, a silicon dioxide dielectric layer over a silicon nitride layer. Then those layers over the tunnel oxide are patterned into flash memory gate electrode by etching through a source/drain mask followed by ion implanting source/drain dopant ions through the openings formed by etching. Sidewall spacers are formed followed by a dielectric layer through which source line openings are etched down to the source/drain regions. Plug openings are made down to the source/drain regions. An intermetal dielectric layer is deposited comprising PEOX/SOG/PEOX over the device. Then via openings are made over the drain plugs by etching the intermetal dielectric layer through a via mask. Next metal is deposited over the intermetal dielectric layer into the via openings extending down into contact with the drain plugs.

Abstract: A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Abstract: A method is provided for producing a dummy pattern for an I.C. semiconductor device multi-layer interconnection metallurgy, having a planar global top surface with a dummy pattern for a circuit for use with conductor lines in the circuit pattern. Create a reverse pattern which is a complement of a widened conductor lines in the circuit pattern with openings about the location of the circuit pattern and provide a dummy cross grid pattern. A gridded dummy pattern is generated by creating a dummy grid pattern of the reverse pattern combining it with the negative of the dummy cross grid pattern leaving a cross grid of dummy elements and openings about the location of the circuit pattern. Provide a revised pattern by adding the circuit pattern to the gridded dummy pattern. Take the product of a contact layout pattern multiplied times the sizing operator multiplied times a separation parameter. Then subtract the sized and separated contact layout pattern from the gridded dummy pattern.

Abstract: An integrated circuit functions as an image detector providing an output signal representing the detected image. A two dimensional array of sensor cells is formed in rows and columns. A digital timing control means has outputs for providing timing signals. An address encoder is coupled to receive timing control signals from the digital timing control means. Each sensor cell has a photodiode and a first transistor having a first gate and having a source/drain circuit for precharging the cell and a second transistor having a second gate and a source/drain circuit for reading from the photodiode. The sensor cells are adapted for sensing electromagnetic radiation incident thereon. A plurality of sensor data amplifiers receives data from the cells. Means is provided for reading data from the cells into the sensor data amplifiers, and the sense amplifiers include an output circuit.

Abstract: A computer operated method comprises a sequence of steps for management of data of a manufacturing operation with workstations in several different functional locations. The manufacturing operation is configured to perform a specific task at each location. Data for lots of work located in containers in the plant is read. The data which has been read is sent through a polling engine for transmission to be collected in a database system. The collected data is then supplied from the database system to a plurality of programmable workstations which are linked to the database by lines in a star network.

Abstract: A reticle, for use in a stepper, and a method for using the reticle are provided. The reticle is used in performing the method for inspecting for the leveling of the reticle with respect to a semiconductor wafer being exposed by the stepper. Reticle alignment marks are used to measure reticle leveling by determining the degree of resolution at several sites on the semiconductor workpiece. The reticle can be patterned with a plurality of sets of alignment marks having an array of blocks which are in focus at different focal lengths. The alignment marks include marks located proximate to the corners of the reticle and proximate to the center of the reticle. Microscope measurements are made to determine the focal length at each set of alignment marks. Reticle pitch is determined at each workpiece position from the focal lengths measured at each alignment mark. The leveling can be checked repeatedly to obtain information for producing optimum focus of the reticle image on the workpiece.

Abstract: An interactive data processing system and/or method is a management tool for a manufacturing plant including a shop floor control system. A server contains a data engine for extracting data, a load and transform data unit, and a database management storage unit. Data from the shop floor control system is supplied to the data engine in the server. The data engine can run the shop floor control system. The data engine supplies data received from the shop floor control system to the load and transform data unit. The load and transform data unit supplies data to the database management storage unit where the data is stored in a disk storage unit in storage space allocated to a conventional database management system employed for the purpose of management of data. The database management storage unit supplies data to an interactive graphic user interface.

Abstract: In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: A workpiece with a back surface and a front surface has a layer formed on the front surface thereof which is to be etched by plasma etching. The workpiece is placed on a lower electrode in a plasma etching system with the back surface resting on the lower electrode. The workpiece is clamped to the lower electrode. A gas circulation system is formed in the surface of the lower electrode to supply heated gas, under pressure, to the back surface of a workpiece placed thereon to cause the workpiece to bow thereby forming a vaulted space below the workpiece. Then, while heating the back of the workpiece in this way, plasma etching of the layer upon the workpiece is performed.

Abstract: A method and system are provided in a software network using a network of disconnected servers for detecting which background data processing functions have stopped running in that network of disconnected servers. The network of disconnected servers is monitored to determine those that contain background data processing functions which have stopped running in servers which remain disconnected. Notification is provided as to which servers have stopped running but remain disconnected and which background data processing functions in the servers have stopped running. The system periodically sends a message to restart servers which contain background data processing functions which have stopped running and remain disconnected.

Abstract: A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate is provided. An N+ source layer is formed on the surface of the semiconductor substrate. A dielectric layer is formed on the surface of the source layer. The dielectric layer is patterned and etched forming a dielectric layer pattern with openings therein, a silicon epitaxial layer in the openings in the dielectric layer pattern. An N+ drain layer is formed on the surface of the silicon epitaxial layer. A second dielectric layer is formed on the surface of the device including the N+ drain layer. A conductor layer is formed and patterned containing silicon over the second dielectric layer. An N+ implant mask with an N+ opening over a region of the epitaxial layer is formed (source) and ion implanting through that N+ opening into the N+ implant mask in that region. A code implant mask over the conductor layer is formed and ions are implanted through the code implant mask into the device.

Abstract: A flash memory EEPROM transistor is formed on a surface of a semiconductor substrate. In portions of the substrate, at the surface thereof, a doped source region and a doped drain region are formed with a channel region therebetween. A tunnel silicon oxide dielectric layer is formed over the semiconductor substrate aside from the source region. Above the source region is formed a gate oxide layer which is thicker than the tunnel oxide layer. Above a portion of the tunnel oxide dielectric layer, over the channel region and above a portion of the gate oxide layer is formed a stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer. The source region is located on one side of the stacked gate structure with one edge of the source region overlapping the gate structure. The drain region which is located on the other side of the stacked gate structure with one edge thereof overlapping the gate structure.

Abstract: An integrated circuit EPROM memory device includes devices to which electrical connections are to be made. A tunnel oxide layer on a semiconductor substrate carries an array of gate stacks with sidewalls with trench spaces therebetween comprising wider drain trench spaces and narrower source trench spaces down to the tunnel oxide layer. Gate stacks include a doped polysilicon floating gate over the tunnel oxide layer, a dielectric layer over the floating gate, a polysilicon control gate over the dielectric layer covered by a silicon dioxide dielectric layer and a silicon nitride layer. Source/drain regions lie between the stacks with alternating source regions and drain regions below the trench spaces between the sidewalls. Spacers are adjacent to the sidewalls of the drain trench spaces. Spacer dielectric plugs fill source trench spaces. A blanket dielectric layer overlies the stacks and the spacer dielectric plugs.

Abstract: This computer system, as well as its method of operation, corrects the position data used to define the location of alignment marks on a workpiece. The first step is to scan marks along a first direction to determine the direction of wafer scaling along the first direction. Second, scan marks along a second direction to determine the direction of wafer scaling along the second direction. Next, scan a first set of alignment marks on a workpiece oriented in a first direction and a second set of alignment marks on the workpiece oriented in a second direction in an initial sequence to collect initial direction data on the location. Then, scan the first set of alignment marks and the second set of alignment marks in a reverse sequence to collect reverse direction data on the location. Finally, average the initial direction data and the reverse direction data. This enables correction of false alignment data attributable to falsely measured locations of alignment marks.

Abstract: A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.