Abstract: An on-line records identification system for users in a multiple-level hierarchy. The system provides a record origin identifier associated with each record, wherein a unique record origin identifier is assigned to each original record. Also provided is a relative identifier associated with each record of a single user at a single level of the hierarchy, wherein a unique relative identifier is assigned to each original record. Further provided are means for transmitting a record from a user at a first level of the hierarchy to a user at a second level of the hierarchy and means for translating the relative identifier associated with the record at the first level to a relative identifier associated with the record at the second level. The on-line records identification scheme is well-suited for a client-server architecture that has separate processing and storage capability at each level of the hierarchy.

Abstract: A dielectric layer over a substrate is covered with a gate conductor mask and an organic polymer lining layer formed on the device narrows the mask opening to create a gate conductor molding trench by MERIE etching through the opening and dielectric down to the substrate. Then a gate oxide layer is formed. A conformal floating gate conductor is deposited over the device and down into the trench, narrowing the trench. A thin interelectrode dielectric layer covers the floating gate and further narrows the trench. A control gate layer covers the device and fills the trench. The floating gate, the interelectrode dielectric, and the control gate conductor are planarized down to the dielectric, which is stripped away. Then self-aligned source/drain regions are formed in the substrate. Semiconductor memory gate conductor stacks have increased surface area for improving the coupling ratio.

Abstract: In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source.

Abstract: An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.

Abstract: A chemical reactant bottle for containing a chemical reactant is adapted for heat transfer with an ambient fluid. The bottle has a body including a top and a bottom and sidewalls between the top and the bottom of the bottle. The top and the bottom and the sidewalls define a cavity within the bottle. There is an opening through the top into the cavity at one end of the bottle. The bottle includes a plurality of external slots extending through the body parallel with the longitudinal axis. The slots extend between the sidewalls of the bottle to create additional contact surface with the ambient fluid.

Abstract: A method and apparatus provide for monitoring and controlling a chemical process with a chemical substance adapted for treatment of a semiconductor device. The chemical substance is held in a container. The process of monitoring is provided by transmitting a light or other electromagnetic energy from a source located within the container through the chemical substance. The electromagnetic energy transmitted through the chemical substance is sensed with a photosensor or a photosensor fiber located within the container. A comparison to a standard is made of the result of the sensing by spectrum analysis, with a passband filter between the source and the photosensor. The sensor may comprise a wavelength adjustable photosensor or a multiple wavelength photosensor.

Abstract: In dynamic dispatching of integrated circuit wafer lots in an integrated circuit fabrication plant, determine the Stage Achievement Rate (SAR) of descendant stages for each candidate stage to be processed by the fabrication plant. With the loading of descendant stages for each candidate stage, determine the Adjusted Loading (AL), where AL=SAR*(Loading of descendant stages for each candidate stage). Determine the Picked Probability (PP) equal to Normalized 1/AL of grouped descendant stages. Determine the Estimated Loading (EL) of descendant stages for each candidate stage. Determine the Estimated Achievement Rate (EAR) of descendant stages for each candidate stage. Next, determine the Estimated Adjusted Loading (EAL) of descendant stages for each candidate stage. Then determine the Total Estimated Adjusted Loading (TEAL) for each candidate stage. Finally, determine the Dynamic Dispatching Order (DDO) of the wafer lots.

Abstract: A method of forming a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate include the following steps. Form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device. Form an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls. Partially etch away the outer dielectric, spacer layer with a dry etch to form a outer dielectric spacer adjacent to the conforming sidewalls. Then partially etch away more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer.

Abstract: A pattern is formed on a substrate by the process of providing a substrate having a surface with previously patterned features having a non-uniform electromagnetic reflectivity, applying a second image recording material to the surface, employing the features with a non-uniform physical property of reflectivity to delineate a desired pattern in the second image recording material and applying electromagnetic energy to take advantage of the reflectivity features to provide variable processing of the second material.

Abstract: A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes.

Abstract: A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

Abstract: A method of forming an SRAM transistor cell on a doped semiconductor substrate with a halo region in transistors thereof by the steps including well formation, field isolation formation, threshold voltage implant, gate oxidation; deposition of polysilicon and patterning thereof into gate electrode; post etching anneal; N type LDD photolithography and ion implanting NMOS transistor devices; ion implant halo regions in a transistor; P type LDD photolithography and ion implanting PMOS transistor devices; spacer formation; N+ source/drain photolithography and ion implanting; and P+ source/drain photolithography and ion implanting.

Abstract: This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

Abstract: A lithographic projection method which comprises projecting radiation along a transmission path and through a lens system and an opaque back focal plane filter for electrons with a transparent aperture for the projected radiation to produce a patterned image and an amount of desired radiation on a target. The transmission path includes a source of radiation of charged particles directed at a target comprising a substrate coated with resist. A pattern-defining mask that contains a plurality of subresolution scattering features thereon to produce the desired degree of scattering of the radiation is placed between the source and the target. The subresolution scattering features vary in density as an direct function of predicted proximity exposure.

Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

Abstract: A method of forming a contact between a conductor and a substrate region in a MOSFET device is provided starting with forming a semiconductor substrate with a silicon oxide layer formed on the surface thereof. Then form a stack of a conductor material upon the surface of the silicon oxide layer and form a first dielectric layer upon the conductor material. Pattern the conductor stack into conductors. Form a butted contact pattern in the first dielectric layer by removal of the dielectric layer in at least one butted contact region. Form doped regions in the substrate self-aligned with the conductors. Form an etch stop layer over the device. Form a second dielectric layer over the device and pattern the second dielectric layer with contact openings therethrough down to the substrate and to the butted contact region. Employ the etch stop layer when patterning the second dielectric layer. Remove exposed portions of the etch stop layer subsequent to patterning the second dielectric layer.

Abstract: A method of operating a batch sequential machine in a manufacturing plant to optimize processing of lots of work through a plurality of series of processing stations which perform various functions comprising the following steps. Collect interval-times (I.sub.i,j) for processing of lots through individual processing stations. Form a matrix of reduced times for processing lots through the processing stations. Determine permutations of the reduced times for a series of combinations of the processing stations for performing required processing tasks. Select the combination of interval-times providing the maximum reduction of total processing time.

Abstract: A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at cross-overs steps and interconnections to avoid open-circuit.

Abstract: A method and system are provided for operating a data processing system including a data base computer system and a resource allocation computer for control of resource allocation in a manufacturing plant with a manufacturing line comprising a plurality of stages with manufacturing machines, the resource allocation computer including data storage means. The method includes several steps including: deriving data from the data storage means and computing the targets for each of the stages; obtaining machine capacity data from the data storage means and employing the machine capacity data for allocating machine capacity proportionally and adjusting targets; adding limits to stages of penetration and adjusting targets; determining residual capacity and allocating the residual capacity of the manufacturing machines; and checking the convergence of targets and machine allocation until convergence is achieved.