Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A method and apparatus for aligning a charged particle beam with an aperture includes providing a hollow beam aperture device adapted for shaping a charged particle beam into a hollow charged particle beam. Then direct the charged particle beam through the aperture. Provide deflection coils for deflecting the charged particle beam relative to the aperture. Vary the current to the alignment deflection coils while measuring the aperture electrical current generated by charged particles reaching the hollow beam aperture as a function of the current to the alignment deflection coils. Then adjust the current in the alignment deflection coils based on the aperture electrical current to center the charged particle beam on the hollow beam aperture. Preferably, separate hollow beam and peripheral beam apertures with associated sensing and current are used to center the beam on respective ones of the apertures.

Abstract: An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the <100> crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the <100> surfaces of the mesas are in contact with the mesas formed on the substrate and that the <110> surfaces of the silicon of the mesas are shielded from the contacts.

Abstract: Calculate the WIPi for a stage STkk for each lot Li in a queue of lots being processed in a production line between the stage STkk and an end point, where “i” is a positive integer representing the position of the lot Li in the queue, and where “kk” is a positive integer indicating the sequential position of the stage STkk (location along the production line) from the beginning to the end of a predetermined portion of the production line. Calculate remaining scheduled cycle time (RCTi) for each lot Li. Calculate consumed scheduled cycle time (CSTi) for each lot Li. Calculate (WIPi*RCTi) for each lot Li. Calculate (WIP*CSTi) for each lot Li. Sum WIPi*RCTi for all lots Li of a stage. Sum WIPi*CST for all lots Li of a stage.

Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.

Abstract: A power supply noise compensation amplifier has an input for connection to a power supply. The amplifier includes a differential amplifier circuit for providing an instantaneous amplified signal in response to power supply noise, and produces an output signal with an instantaneous opposite polarity from the power supply noise so a noise sensitive circuit connected to the noise compensation amplifier has a compensated power supply signal which enables it to produce a reduction in the amplitude of the noise signal at the output thereof. The differential amplifier circuit includes a differential pair of coupled transistor circuits including a leading transistor circuit and a lagging transistor circuit.

Abstract: This is a method for designing an optimized charged particle beam projection system. Specify lens configuration and first order optics. Calculate lens excitations. Configure the lens system, providing lens field distributions, beam landing angle, and imaging ray/axis cross-over. Provide an input deflector configuration. Solve a linear equation set, and thereby provide a curvilinear axis and associated deflection field distributions. Calculate the third order aberration coefficients yielding a list of up to 54 aberration coefficients. Provide an input of dynamic correctors. Calculate excitations to eliminate quadratic aberrations in deflection. Calculate third and fifth order aberrations, providing image blur and distortion vs. deflection, best focal plane, and depth of focus. Determine whether the current result is better than the previous result. If YES then change the axial location input to the solve linear equation set. If NO, test whether the current result is acceptable.

Abstract: To form a spin valve device, start by forming a gap layer. Form a buffer layer with a layer of refractory material on the buffer layer. Form patterned underlayers including a magnetic material for providing trackwidth and longitudinal bias on the buffer layer comprising either a lower antiferromagnetic layer stacked with a ferromagnetic layer or a Cr layer stacked with a permanent magnetic layer. Form an inwardly tapered depression in the patterned underlayers down to the buffer layer by either ion milling through a mask or a stencil lift off technique. Form layers covering the patterned underlayers that cover the inwardly tapered depression. Form free, pinned, spacer and antiferromagnetic layers. Form conductors either on a surface of the antiferromagnetic layer aside from the depression or between the buffer layer and the patterned underlayers.

Abstract: A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.

Abstract: A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows. A set of trenches are formed with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer.

Abstract: A dynamic mask exposure method and system includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transparent as a function of control inputs to the actuator lines, the transmissive dynamic mask having a top surface and a bottom surface. A control system is connected to supply pixel control signals to the actuator lines of the transmissive dynamic mask to form a scanning pattern of transparent regions and opaque regions which scans across the dynamic mask. The beam is directed down onto the top surface of the mask and through a slit in a diaphragm onto the workpiece. The beam passes through the transparent regions and projects a pattern from the mask onto the support where the workpiece.

Abstract: A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric layer. A doped silicon semiconductor substrate is covered with variable thickness silicon oxide regions on the surface thereof with junctions between the variable thickness regions. The silicon oxide regions are substantially thicker beneath the center of the floating gate electrode. Source/drain regions formed in the substrate extend beneath the tunnel oxide regions with the junctions aligned with the regions. The floating gate electrodes formed over the silicon oxide regions above the source/drain regions including dielectric sidewalls within the floating gate electrode above the junctions. The variable thickness silicon oxide regions are tunnel oxide regions on either side of a gate oxide region.

Abstract: A bubbler for use in vapor generation systems that minimizes splashing and the formation of aerosol droplets of liquid, which are carried out of the bubbler in the vapor stream and result in erratic mass transfer of the process chemical liquid. A closed stainless steel vessel contains a carrier gas distribution plenum that distributes the carrier gas to a plurality of small diameter generator tubes, which are submerged into the process chemical liquid. The length, inside diameter and number of the generator tubes are designed to inject a high velocity, small diameter stream of carrier gas into the liquid such that a long small diameter cylinder of carrier gas is created in the process chemical liquid. The surface tension of the liquid-gas interface causes the cylinder of gas to be pinched off at intervals along the length of the cylinder to produce a plurality of small bubbles the diameter of which is largely independent of the carrier gas flow rate.

Abstract: In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Then form a mask over the stack and etch through the mask to pattern the oxide layers to form cavities in the stack of oxide layers reaching down through the stack to the sublayer. Then perform differential etching of the oxide layers in the cavities. Form undercut edges in the doped oxide layers with the undoped oxide layers having cantilevered ribs projecting from the stacks into the cavities to complete the cavities. Deposit a bulk/thick film monolithic conductive layer into the cavities to form a monolithic capacitor core with counterpart cantilevered ribs.

Abstract: A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

Abstract: RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.