Abstract: A method of forming a mask from a metal layer deposited upon a substrate patterned for exposure of a workpiece to radiation of a specific range of wavelengths with the substrate being transparent to the radiation comprises the following steps. Form the metal layer superjacent to the substrate. Form a photoresist layer superjacent to the metal layer. Expose the photoresist layer to a pattern. Develop the photoresist to Form a photoresist mask with an opening therethrough. Bake the photoresist mask, the metal layer and the substrate. Perform a descum operation. Perform an isotropic etching of the metal layer through the opening in the mask. Perform an after etching inspection measurement. Strip the photoresist mask. Perform an after stripping inspection measurement. The isotropic etching is performed with a wet etchant. The descum operation is performed with a dry plasma process including oxygen and nitrogen gases and an inert gas selected from argon and helium.

Abstract: This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.

Abstract: Form a solder connector on a semiconductor device starting with a first step of forming at least one dielectric layer over a doped semiconductor substrate. Then form a hole through the dielectric layer down to the semiconductor substrate. Form a metal conductor in the hole. Form intermediate layers over the metal conductor and the dielectric layer. Then form a tapered opening down to the surface of the metal conductor. Form BLM layers including a titanium-tungsten (TiW) layer over the metal conductor and the dielectric layer with the remainder of the BLM layers being formed over the TiW layer. Form a mask over the top surface of the BLM layers with a patterning through hole located above the metal conductor exposing a portion of the surface of the BLM layers. Plate a C4 solder bump on the BLM layers in the patterning hole. Remove the mask. Wet etch away the BLM layers aside from the solder bump leaving a residual TiW layer over the dielectric layer.

Abstract: A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes.

Abstract: A method and system are provided for determining the degree of overlay misregistration when exposing a semiconductor wafer having a center and a periphery comprises the following steps. Expose the wafer with a scan in a sequence from the center of the wafer to the periphery. Select dies on the periphery of a wafer for measurement which represent a maximum degree of distortion, and employ a correction algorithm for calculating an intrafield reduction ratio to minimize heat expansion.

Abstract: An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating layer is more free of pin-holes. After the insulating layer in the thin oxide region of the TFT is etched away, conventional fabrication processes are followed. The dielectric of the thin film oxide region is the same as that of the conventional TFT; but the dielectric in the vicinity of the thin oxide region, the crossovers of the data lines and the scan lines, and the gate dielectric layer of the TFT are now composed of the high quality insulating layer. The TFT structure can improve the yield of fabrication by confining the channel region in the shadow of the gate electrode to reduce the leakage photo-current, and by reducing the steps at crossovers steps and interconnections to avoid open-circuit.

Abstract: A dynamic mask exposure system and method includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic phase-shifting mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transparent as a function of control inputs to the actuator lines. The transmissive dynamic mask has a top surface and a bottom surface. A control system is connected to supply pixel control signals to the actuator lines of the transmissive dynamic mask to form a pattern of transparent regions and opaque regions. The beam is directed down onto the top surface of the mask. A workpiece and/or an image detection element for detecting a pattern of radiation projected thereon is located on the top surface of the support. The beam passes through the transparent regions and projects a pattern from the mask onto the support where the workpiece or onto the image detection element is to be located.

Abstract: A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu3Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.

Abstract: This method and apparatus permit installing and removing an electron beam generating element comprising a filament or a cathode in a rapidly replaceable module. The apparatus is an electron gun system having an electron gun enclosure, a feed-through element extending through the electron gun enclosure, an electron beam generating element housed within a filament module housing and connected to the feed-through element, an electron gun column and a connector port in the gun enclosure for direct removal and replacement of the filament. The feed-through element and the filament module housing are removed, through the connector port, from the gun enclosure and then the filament is removed and replaced. A load-lock is provided above the connector port to avoid venting into the gun. A bellows can be used to facilitate removal of the gun with minimal exposure to ambient atmospheric gases.

Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

Abstract: This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to the well. Form an intermediate conductor layer and a hard silicon oxide mask layer and define gate conductors. Form lightly doped source/drain regions, form spacers and source/drain regions in the well. Form a first inter-conductor dielectric layer on the cell. Define a self-aligned contact region in the cell above source/drain regions. Form a second conductor layer over the cell and patterning the second conductor layer to form a via in the self-aligned contact region. Form a second inter-conductor dielectric layer on the cell, a third conductor layer over the cell and patterning the third conductor layer to form a first resistor connected to the self-aligned contact region.

Abstract: In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: An off axis illumination stepper exposure system includes an illumination system with an aperture element and lenses. The aperture element comprises an array of electronically switchable pixels in a matrix. The aperture element can be a transmissive spatial light modulator. An annular pattern of transmissivity through an aperture element is provided by a spatial light modulator operated under computer control. The computer can select and provide variable dimensions of the pattern to optimize operation of the device. In addition to a first transmissive spatial light modulator providing an aperture in the illumination system with a pattern of transmissivity operated under computer control, a mask is provided in the form of a second transmissive spatial light modulator operated under computer control operating cooperatively to provide images projected through a projection system onto a workpiece supported upon a stepper tool.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

Abstract: A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for a producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

Abstract: A method for forming a longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises forming a first patterned magnetoresistive (MR) layer. Contact the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer, each of the stacks including a first Anti-Ferro-Magnetic (AFM) layer and a first lead layer. Then anneal the device in the presence of a longitudinal external magnetic field. Next, form a second patterned magnetoresistive (MR) layer above the previous structure. Contact the opposite ends of the second patterned magnetoresistive (MR) layer with a second pair of stacks defining a second track width of the second patterned magnetoresistive (MR) layer. Each of the second pair of stacks includes spacer layer composed of a metal, a Ferro-Magnetic (FM) layer, a second Anti-Ferro-Magnetic (AFM) layer and a second lead layer.

Abstract: Variable space charge effects in the imaging portion of a particle beam projection system due to variations in transmitted beam current are compensated with an additional lens appropriately positioned within the imaging system and having a focal length which varies in response to the transmitted beam current.

Abstract: A method of forming an SRAM transistor cell on a doped semiconductor substrate with a halo region in transistors thereof by the steps including well formation, field isolation formation, threshold voltage implant, gate oxidation; deposition of polysilicon and patterning thereof into gate electrode; post etching anneal; N type LDD photolithography and ion implanting NMOS transistor devices; ion implant halo regions in a transistor; P type LDD photolithography and ion implanting PMOS transistor devices; spacer formation; N+ source/drain photolithography and ion implanting; and P+ source/drain photolithography and ion implanting.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.