Patents Represented by Attorney Gray Cary Ware & Freidenrich, LLP
  • Patent number: 6789250
    Abstract: A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Watanabe, Mitsuhiro Yano
  • Patent number: 6788608
    Abstract: A digital multilevel non-volatile memory integrated system includes an apparatus and method for high voltage, high precision pulsing generation. A voltage generator includes a low voltage high speed generator, a low voltage to high voltage high speed level translator, and a high voltage driver. A precise and stable high voltage level is attained across power supply, process, or temperature variation. The power may be optimized at the high voltage supply as tradeoff with power in the low voltage supply. A ping-pong operation sets up a high voltage level and the high voltage pulsing is output in a ping-pong fashion. A slew rate control circuit slows the input to achieve faster settling times. The high voltage is shaped by low voltage switching, HV fast switching and ramp circuit control. The high voltage pulsing may be fast and precise to permit real time control of the pulse parameters to adapt to memory cell attributes.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: September 7, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, William John Saiki, Jack Edward Frayer, Michael Stephen Briner
  • Patent number: 6788595
    Abstract: Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: September 7, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hung Q. Nguyen, Sang Thanh Nguyen, Loc B. Hoang, Tam M. Nguyen
  • Patent number: 6789152
    Abstract: A storage router (56) and storage network (50) provide virtual local storage on remote SCSI storage devices (60, 62, 64) to Fiber Channel devices. A plurality of Fiber Channel devices, such as workstations (58), are connected to a Fiber Channel transport medium (52), and a plurality of SCSI storage devices (60, 62, 64) are connected to a SCSI bus transport medium (54). The storage router (56) interfaces between the Fiber Channel transport medium (52) and the SCSI bus transport medium (54). The storage router (56) maps between the workstations (58) and the SCSI storage devices (60, 62, 64) and implements access controls for storage space on the SCSI storage devices (60, 62, 64). The storage router (56) then allows access from the workstations (58) to the SCSI storage devices (60, 62, 64) using native low level, block protocol in accordance with the mapping and the access controls.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 7, 2004
    Assignee: Crossroads Systems, Inc.
    Inventors: Geoffrey B. Hoese, Jeffry T. Russell
  • Patent number: 6783933
    Abstract: A novel T-type calcium channel (CACNA1G) is provided, as are polynucleotides encoding the same. CACNA1G has been implicated in cellular proliferative disorders. More specifically, it has been observed that the methylation state of specific regions within CpG island associated with the CACNA1G gene correlates with a number of cancerous phenotypes involving a variety of tissue and cell types. Also provided are methods for detecting cellular proliferative disorders by determining the methylation state of genes or regulatory regions associated therewith, including CACNA1G, as well as kits containing reagents for performing invention methods.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: August 31, 2004
    Assignee: The Johns Hopkins University School of Medicine
    Inventor: Jean-Pierre Issa
  • Patent number: 6783919
    Abstract: The invention relates to a TFT-LCD high-performance stripper composition for a photoresist, and more particularly to a stripper composition for a photoresist comprising: 20-60 wt % of monoethanolamine, 15-50 wt % of N,N-dimethylacetamide, 15-50 wt % of carbitol, and 0.1-10 wt % of gallic acid. The invention also provides a stripper composition for a photoresist comprising: 20-60 wt % of monoethanolamine, 15-50 wt % of N,N-dimethylacetamide, and 15-50 wt % of carbitol. The stripper composition for a photoresist of the invention significantly reduces stripping time when applied to the TFT-LCD manufacturing process and leaves no impurity particles. By allowing the hard baking and ashing processes to be omitted, the gate process line can be simplified, which enables cost reduction. In addition, when it is applied to a process wherein silver (Ag) is used as reflective/transflective layer, it offers stripping ability and corrosion resistance of the pure Ag layer.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 31, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sik Park, Sung-Chul Kang, Hong-Je Cho, An-Na Park
  • Patent number: 6780856
    Abstract: The invention relates to methods of stabilizing in an aqueous medium cobalt (III) Schiff base complexes and stabilized cobalt (III) Schiff base compounds therefrom.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: August 24, 2004
    Assignee: California Institute of Technology
    Inventors: Thomas J. Meade, Ofer Blum, Harry B. Gray
  • Patent number: 6782440
    Abstract: Systems and methods are described for resource locking and thread synchronization in a multiprocessor environment. One method includes restricting access to a protected shared resource by use of a lock; issuing the lock to a requesting software to permit access to the protected shared resource; indicating the issuance of the lock to the requesting software by writing a first value to a lock register; freeing the lock, thereby making the lock available for use by another requesting software, after the requesting software completes accessing the protected shared resource; and indicating that the lock is free by writing a second value to the lock register.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: August 24, 2004
    Assignee: T.N.S. Holdings, Inc.
    Inventor: Chris D. Miller
  • Patent number: 6782016
    Abstract: Systems and methods are described for laser array synchronization using master laser injection of broad area lasers. A method, includes: master laser injecting a plurality of broad area lasers; and externally cavity coupling the plurality of broad area lasers. A method, includes: master laser injecting a plurality of broad area lasers; and externally Q switch coupling the plurality of broad area lasers. A method, includes: injection synchronizing a plurality of pulsed broad area lasers using a signal source; modulating the plurality of pulsed broad area lasers using the signal source; and externally coupling the plurality of pulsed broad area lasers.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 24, 2004
    Assignee: UT-Battelle, L.L.C.
    Inventors: Yehuda Y. Braiman, Yun Liu
  • Patent number: 6781576
    Abstract: A wireless input apparatus by which a user can input various types of information is provided. A conventional remote control of electronic equipment has many buttons or switches to perform various kinds of functions. Therefore, its operability is likely to be lost because of the complexity and the bulkiness of the remote control. The wireless input apparatus has a LCD to display a screen for operation and a 3-D mouse for a user to operate. The user can input various types of operations on the screen and remotely control the equipment. Moreover, a pressure-sensitive resistance film is applied to the 3-D mouse for sensing pressure applied by the user. Even if a very slight amount of pressure is applied to the mouse, the pressure can be effectively detected.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: August 24, 2004
    Assignee: Sensation, Inc.
    Inventor: Yasuhiro Tamura
  • Patent number: 6780975
    Abstract: Engineered fluorescent proteins, nucleic acids encoding them and methods of use are provided.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: August 24, 2004
    Assignees: The Regents of the University of California, Vertex Pharmaceuticals (San Diego) LLC, State of Oregon Acting by and through the State Board of Higher Education on behalf of the University of Oregon
    Inventors: Roger Y. Tsien, S. James Remington, Andrew B. Cubitt, Roger Heim, Mats F. Ormö
  • Patent number: 6780418
    Abstract: A method of detecting a member of the taxa actinomycetos is provided. A method also is provided for detecting mycothiol or precursor thereof. An antibody is provided which binds to mycothiol or a mycothiol precursor. A method is further provided for diagnosis of a subject having or at risk of having an actinomycetes-associated disorder. A method is also provided for identifying a sample with altered production of mycothiol or a precursor thereof. A method is provided for detecting mycothiol or precursor thereof in a bacterial colony. Kits are also disclosed which arc useful for detecting the presence of mycothiol or precursor thereof in a sample.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: August 24, 2004
    Assignee: The Regents of the University of California
    Inventors: Robert C. Fahey, Gerald L. Newton, Maria Margarita D. Unson, Charles E. Davis, Sara J. Anderberg
  • Patent number: 6780600
    Abstract: Disclosed are nucleotide coding sequences and polypeptide sequences for synaptic activation binding proteins that are characterized by induction in the central nervous system following neuronal activity in rat hippocampus. Such proteins are identified by (i) substantial homology at the nucleotide or protein sequence level to specifically defined rat, human or mouse coding sequences or proteins, (ii) ability to bind to and affect the activity of effector proteins in the CNS, such as metabotropic glutamate receptors, (iii) binding specificity for a particular binding sequence, and (iv) presence in the sequence of a PDZ-like domain. Nucleotides and polypeptides of the invention are useful in screening and diagnostic assays.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: August 24, 2004
    Assignee: The Johns Hopkins University School of Medicine
    Inventors: Paul F. Worley, Paul R. Brakeman
  • Patent number: 6777260
    Abstract: A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: August 17, 2004
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Bomy Chen
  • Patent number: 6779167
    Abstract: An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Masaaki Yamada, Koji Hashimoto, Makoto Takashima, Atsuhiko Ikeuchi
  • Patent number: 6777405
    Abstract: Duplex polynucleotides containing damage or errors are detected with hindered intercalating compounds which are capable of intercalating only in the presence of such damage or error. Conditions characterized by the presence of polynucleotide errors or damage are treated with such compounds that are capable of catalyzing polynucleotide cleavage with light.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: August 17, 2004
    Assignee: California Institute of Technology
    Inventors: Jacqueline K. Barton, Brian A. Jackson, Brian P. Hudson
  • Patent number: 6777999
    Abstract: In a master block, the exponential conversion characteristic is determined on the basis of a common mode reference voltage and a reference voltage. In a slave block, the exponential conversion characteristic determined with the master block is used to create a control voltage and a gain control signal on the basis of a common mode reference voltage and a reference voltage. For example, a gain of the variable gain amplifier is controlled by using this gain control signal.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Kanou, Takafumi Yamaji, Tetsuro Itakura
  • Patent number: 6777966
    Abstract: The cleaning device may clean probe elements. The probe elements may be the probe elements of a probe card testing apparatus for testing semiconductor wafers or semiconductor dies on a semiconductor wafer or the probe elements of a handling/testing apparatus for testing the leads of a packaged integrated circuit. During the cleaning of the probe elements, the probe card or the handler/tester is cleaned during the normal operation of the testing machine without removing the probe card from the prober. The cleaning device may be placed within the prober or tester/handler similar to a wafer containing semiconductor dies to be tested so that the probe elements of the testing machine contact the cleaning medium periodically to remove debris and/or reshape the tips of the probe elements.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: August 17, 2004
    Assignee: International Test Solutions, Inc.
    Inventors: Alan E. Humphrey, Billie Jean Freeze
  • Patent number: 6775193
    Abstract: The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to “mask out” any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: August 10, 2004
    Assignee: GIGA Semiconductor, Inc.
    Inventors: Taiching Shyu, Lee-Lean Shu
  • Patent number: D494393
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: August 17, 2004
    Assignee: Wonderland Nursery Goods Co., Ltd.
    Inventor: Shun-Min Chen