Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.

Abstract: In an embodiment, a quantity smoother includes a first stage and a second stage. The first stage is operable to receive a sequence of raw samples of a quantity and to generate from the raw samples intermediate samples of the quantity, the intermediate samples having a reduced level of fluctuation relative to the sequence of raw samples. The second stage is coupled to the first stage and is operable to generate from the intermediate samples resulting samples of the quantity, the resulting samples having a reduced level of fluctuation relative to the sequence of intermediate samples. For example, such a quantity smoother may be part of a target-ranging system on board a fighter jet, and may smooth an error in an estimated target range so that the fighter pilot may more quickly and confidently determine in his head a range window within which the target lies.

Abstract: A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.

Abstract: A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.

Abstract: A low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized CAM cell groups, each CAM cell group having one or more CAM cells; a valid entry tag bit associated with each said content addressable memory cell; a match output generator connected to the output of each CAM cell and an enabling means having its first input connected to the valid entry tag bit, its second input connected to a match control signal and its output connected to the corresponding match output generator such that said match output generator is enabled only if said valid entry tag bit indicates a valid entry.

Abstract: A mid-infrared emitter sub-system includes a heat sink and a diamond thermal diffusion layer connected to the heat sink through a first thermal bonding layer. The first thermal bonding layer has a first melting point. A semiconductor slab portion of a semiconductor laser is connected to the diamond thermal diffusion layer through a second thermal bonding layer. The second thermal bonding layer has a second melting point that is less than the first melting point.

Abstract: Integrated optical network comprising: an array of optical waveguides having respective output ends defining a array of radiating elements, wherein said guides receive respective optical input signals and output said optical signals from said radiating elements to form an optical beam; and actuator means to introduce in said array of guides relative phase differences between said optical signals in order to deflect the optical beam formed; characterized in that the actuator means include at least one actuator track comprising a plurality of track sections substantially aligned with respective optical guides, said sections being fed by a common control signal to locally modify refractive indexes of the respective optical guides in order to introduce said phase differences.

Abstract: A system and method of transmitting data packets. The system determines one or more system conditions of the server computer and modifies a process of transmitting the data packets from a server computer to a client computer, the modifying based at least in part upon the determined system conditions. The determined system conditions can include: (i) the number of forced processings of network events, (ii) the number of clients computers that are behind their scheduled delivery time, (iii) the number of client computers that have requested streamable data objects, (iv) the total byte count of the streamable data objects that have been requested by the client computers, (v) the number of the streamable data objects that have been requested by the client computers, (vi) the number of streamable data objects that are maintained by the streaming media server, and/or (vii) the actual transmission rate of the streaming media server with respect to the client computers.

Abstract: The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16kB and even overcoming by at least 2kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.

Abstract: Video game systems for multiple-player games may exchange synchronizing data through the Internet or other data transmission link. These status data records keep the video game systems synchronized with each other whenever different players are trying to use the same virtual tunnel, cave, or other confined room with insufficient space for more than one player character at a time.

Abstract: Conduction loss in the body-diode of a low side MOSFET of a power switching stage of one phase of a coupled-inductor, multi-phase DC-DC converter circuit, associated with current flow in the output inductor of that one phase that is induced by current flow in a mutually coupled output inductor of another phase, during normal switching of that other stage, is effectively prevented by applying auxiliary MOSFET turn-on signals, that coincide with the duration of the induced current, to that low side MOSFET, so that the induced current will flow through the turned-on low side MOSFET itself, thereby by-passing its body-diode.

Abstract: The invention relates to an orbital friction welding method and a friction welding device for welding workpieces by means of friction welding units, wherein the workpieces are pressed against each other in the contact plane during the application of the oscillation energy. To this effect, n>1 friction welding heads are mounted, in a stationary manner, at least on one side of the contact plane in an orbital plane, in the area of the workpieces so that the n>1 friction welding heads, respectively facing one side, are oscillated with the same friction frequency, the same amplitude and the same preset phase position.

Abstract: A method of compressing digital images acquired in CFA format that utilizes optimized quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase that precedes compression, appropriately modifies the coefficients of any initial quantization matrix, even of a standard type, obtaining a greater compression efficiency without introducing further quality losses.

Abstract: A method for decoding-decompressing a compressed-encoded digital data sequence relating to at least one compressed-encoded digital image and for providing at least one respective decoded-decompressed digital image.

Abstract: A constant-on-time power-supply controller includes an adder and a control circuit. The adder generates a sum of a sense voltage and a regulated output voltage generated by a filter inductor. The sense voltage is generated by a sense circuit that sources a current to the filter inductor while the inductor is uncoupled from an input voltage, and the sense voltage is related to the current. The control circuit couples the filter inductor to the input voltage for a predetermined time in response to the sum having a predetermined relationship to a reference voltage. Such a power-supply controller may yield a relatively tight regulation of the output voltage even with a power supply having with a low-ESR filter capacitor, and may do so with little or no additional compensation circuitry as compared to prior controllers and with no additional pin on the power-supply-controller chip.

Abstract: A food analyzer which can be installed on a self-propelled food loading unit, and which includes an optoelectronic device for determining the spectrum of electromagnetic radiation reflected and/or absorbed by a foodstuff loaded by the self-propelled unit; and a processing unit for determining, as a function of the acquired spectrum of electromagnetic radiation, chemical and physical information relative to the elements in the foodstuff.

Abstract: In an aspect of the invention, a device for purifying water in a water water garden or fish pond comprises a filter medium configured to clean the water flowing through the device, and a housing configured to contain the filter media. The housing includes a wall configured to whirl the water flowing through the device to remove suspended particulates from the flow. Liquid flows into the housing, is turned by the wall to whirl the water about an axis, and exposed to elements held by the filter medium for cleaning the liquid. The liquid then flows out of the housing. Cleaning the medium is performed by opening a drain port and adding water to the chamber.

Abstract: An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body region and the drain region formed in the semiconductor material layer. The source and drain regions are spaced apart from each other by a channel zone in a portion of the body region underlying the insulated gate, and a charge carriers drift portion of the semiconductor material layer between the channel zone and the drain region, the insulated gate extending over the charge carriers drift portion. The drain region is located at a depth compared to the front surface for causing charge carriers to move in the charge carriers drift portion away from an interface between the semiconductor material layer and the gate dielectric.

Abstract: In a pressure vessel, pressure fitting, or pressure component, service use may result in the propagation of fatigue cracks. According to embodiments, a leak channel may be designed and formed to cause a pressurized fluid nominally contained by the pressure member to leak after formation of a fatigue crack, rather than undergoing a more catastrophic burst failure. According to an embodiment, a method is taught for determining the propensity of fatigue cracks to form, determining the location of the possible fatigue cracks, and determining a location for a leak channel, leak hole, weep hole, etc. for preventing burst failure. According to an embodiment, a computer program performs steps to design leak channels for prevention of burst failures in favor of leak-before-burst (LBB) failures.