Abstract: Methods and compositions for the treatment, control or prophylaxis of a viral infection in a mammal, the method including administering to the mammal an effective amount of galactofucan sulfate from Undaria.

Abstract: A large-waterplane-area ship operable to efficiently operate at a high-Froude velocity. In one embodiment of the invention, a large-waterplane-area ship includes a hull structure having a plurality of exclusive hull portions protruding from a main body of the hull structure. Each hull portion has a length shorter than the length of the main body and each hull portion has a buoyancy wherein the combined buoyancy of each hull portion is sufficient to support the main body above a waterline. As such, each hull portion acts independently and exclusively of other hull portions with respect to the effects of wave drag. Therefore, the ship overcomes wave drag at lower velocities.

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract: A magnetic adsorption device comprises: a magnetic circuit block having a cavity extending in one direction and divided into a plurality of magnetic pole members at intervals in the circumferential direction of the cavity by a plurality of spacers; and a permanent magnet assembly having an N pole and an S pole and capable of rotating selectively at a first and a second positions spaced apart about an axis of the cavity so as to adsorb and release a magnetic substance. Adjoining spacers about the axis are distant by an angular space of less than 180° about the axis.

Abstract: A goggle comprising a single-eye lenses, a frame, a lens-retention mechanism and an adjustment mechanism wherein the single-eye lenses can be selectively moved relative to the frame to at least two different positions defining substantially different levels of air flow between the single-eye lenses and frame while maintaining the single-eye lenses in front of a user's eyes, and retained at each position. In certain embodiments, one position is defined by substantially all of the single-eye lenses periphery contacting the frame to substantially form a seal. Other positions are defined by substantially all of the lens periphery not contacting the frame wherein ambient air is allowed to flow uninhibited across the inside surface of the single-eye lenses.

Abstract: A quick release ladder leveler attachment system. So that a leveler may be mounted or released from the rails of a ladder quickly and without requiring the use of tools, a leveler attachment structure is added to the lower outer surface of the ladder rails. It may be integrated with the ladder rails or attached to ladder rails with bolts or rivets. The attachment structures include surfaces that engagingly mate with mounting structures on the leveler. The attachment and mating structures may be a keyhole slot and a knob. A spring catch may retain the leveler in place and a locking pin may be added to ensure safety.

Abstract: A computerized method for determining a tilt parameter of a cutting head of a fluid-jet apparatus. The method includes receiving a target-piece shape, describing an ordered path defining the target-piece shape, and segmenting the path into small straight lines of approximately equal length. The method further includes determining a cutting-head translation speed for each of the small straight lines, determining a tilt parameter of the cutting head with respect to the plane of the workpiece in response to the speed and a fluid jet-shape parameter for each of the small straight lines, storing the small straight lines and the determined tilt parameter associated with each small straight line in a memory, and sending the stored data to the fluid-jet apparatus. The method may include controlling the tilt of the cutting head in accordance with the tilt parameter for each small straight line as the cutting head cuts the workpiece.

Abstract: An anoscope for use with a medical instrument insertable within the interior of the anoscope. The anoscope comprises a tubular member having a longitudinal axis with a proximal end and a distal end. The distal end is insertable into the rectum of a patient while the proximal end remains outside the body. A first longitudinal slot extends from the distal end toward the proximal end, and a second longitudinal slot extends from the proximal end toward the distal end. The first and second longitudinal slots are separated by about 180° on the surface of the tubular member. The first longitudinal slot is adapted to permit access to a site to be treated within the rectum and the second longitudinal slot is adapted to accommodate pivoting of the medical instrument at an angle to the longitudinal axis of the tubular member to improve access to the site to be treated.

Abstract: A memory cell includes a volatile circuit operable to store first data, and a nonvolatile circuit coupled to the volatile circuit and operable to store second data. The volatile circuit is operable to program the nonvolatile circuit with the first data, and the nonvolatile circuit is operable to program the volatile circuit with the second data.

Abstract: A semiconductor memory comprises a plurality of memory cells, for example Flash memory cells, arranged in a plurality of lines, and a plurality of memory cell access signal lines, each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

Abstract: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is used to determine the magnitude of the errors in the received digital code word. Each step is divided into m small tasks where m is the number of computational blocks it takes to read in a code word and the processor can pipeline or parallel process one task from each step each time a block is read.

Abstract: A programmable oscillator comprises a capacitor; a current generator couplable to said capacitor that generates a charging current of said capacitor; further comprising at least one resistance coupled to said capacitor; a comparator coupled to said capacitor for comparing a voltage at the terminals of said capacitor with a prefixed reference voltage and for generating an output signal; a first switch, controlled by said output signal, coupled to said capacitor that creates a current path able to facilitate the discharging of said capacitor.

Abstract: A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively. Furthermore, the memory system comprises a first and a second conduction line which can be connected to said first and second column lines, and generating means provided with at least a first and a second output line, making available a first and a second reading/writing voltage to said first and second terminal respectively. The memory system also comprises at least a first and a second selection transistor connected to the same command line and having corresponding operative terminals connected directly to the first and to the second output lines respectively and corresponding cell terminals connected directly to the first and to the second conduction lines respectively.

Abstract: A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.

Abstract: A method of enhancing a source image for analysis. The method comprises the steps of digitizing the source image to obtain pixel data comprising location data and density data, generating a three-dimensional model of the pixel data with the location data represented in first and second axes and the density data represented in a third axis, and analyzing the three-dimensional model to determine features of the source image.

Abstract: A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

Abstract: A basic stage for a charge pump circuit having at least an input terminal and an output terminal and comprising: at least a first inverter inserted between said input and output terminals and comprising a first complementary pair of transistors, defining a first internal node, at least a second inverter inserted between said input and output terminals and comprising a second complementary pair of transistors, defining a second internal node, respective first and second capacitors connected to said first and second internal nodes and receiving first and second driving signals; the first and second pairs of transistors having the control terminals cross-connected to the second and first internal nodes. Advantageously, the basic stage comprises at least a first biasing structure connected to the first and second internal nodes and comprising first and second biasing transistors, which are respectively coupled to said first and second inverters.

Abstract: A phase-lock loop which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase-frequency detector receiving and comparing the oscillator signal and a reference signal from the master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A first window circuit counts the number of comparing cycles of the detector and provides a first window signal for the transmission of the error correction signals from the detector to the oscillator at a frequency of a predetermined number of counted comparing cycles. A second window circuit which, in response to at least the oscillator signal, narrows the first window signal to limit the duration of the correction signal for irregular reference signals.