Abstract: A gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.

Abstract: A body of semiconductor material of a Group III-V compound or alloy of such compounds includes a substrate of one conductivity type with a pair of spaced, substantially parallel, dove-tail shaped grooves in a surface thereof. Over the surface of the substrate and the grooves are, in sequence, a first epitaxial layer of the one conductivity type, a second epitaxial layer which is the active recombination layer, a third epitaxial layer of the opposite conductivity type and a fourth epitaxial layer of the opposite conductivity type. The first and third layers are of a material forming heterojunctions with the second active layer. The second active layer has a region of uniform thickness directly over the space between the grooves. A stripe contact is provided on the fourth layer directly over the region of minimum thickness of the second active layer.

Abstract: A method of fabricating a semiconductor device comprising the steps of disposing a layer of dopant material over exposed portions of a surface of a semiconductor body and over portions of a masking layer adjacent the exposed portions, the dopant material having a diffusion coefficient through the masking layer at least about as large as its diffusion coefficient into the body. The dopant material is selectively etched to remove portions overlying the masking layer and thereafter remaining portions of the masking layer are etched to remove any dopant material which might still remain thereover.

Abstract: A diffusion apparatus, particularly useful for diffusing aluminum into semiconductor wafers, comprises a quartz evaporation tube in combination with a restrictor plate which is inserted in an open end thereof. The restrictor plate preferably has substantially the same shape as, but a slightly smaller cross-section than, the evaporation tube. In practice, the relatively small gap between the restrictor plate and the evaporation tube results in a substantially negligible leak in the diffusion apparatus. As a result the apparatus effectively operates as if it were a sealed ampule while in fact it is open, i.e. not sealed.

Abstract: A gate electrode which is common to at least two CCD channels is formed with a "window" over one of the channels. A second gate electrode over the first controls the substrate potential of the one channel through the window but has no effect on the substrate potential of the other channel. The structure makes it possible to block or delay the propagation of charge in one channel relative to the other and is useful, for example, in structures for parallel-to-serial charge signal translation and vice versa.

Abstract: A method of optically testing electrical parameters of a surface of a semiconductor including carrier mobility and recombination time is disclosed which includes the step of irradiating the surface with a first beam of monochromatic light having a wavelength less than the wavelength corresponding to the band-gap energy of the semiconductor, resulting in the excitation of electrons and holes at the semiconductor surface. The surface is simultaneously irradiated with a second beam of monochromatic light having a wavelength larger than the wavelength corresponding to the band-gap energy of the semiconductor, whereby part of the second beam is reflected from the surface. The intensity of this reflected beam is measured and the magnitude thereof is a measure of the carrier mobility and recombination time at the semiconductor surface.

Abstract: The bit lines of a word organized memory array are precharged to a potential which is substantially equal to the flip points (i.e. the point at which the cell changes state) of the memory cells of the array prior to each read and each write operation. This ensures the non-disturbance of the unselected memory cells of the array, provides greater design freedom of the memory array components, and enables the memory array to operate faster and more reliably.

Abstract: Analog signal is translated to charges which concurrently are spilled down a plurality of charge coupled device (CCD) channels. The CCD storage electrodes of these channels define potential wells at least some of which are of different size and the number of wells in each channel which receive charge as it attempts to fill the successive wells in that channel with depend upon the analog signal amplitude and the respective sizes of said successive wells. The presence or absence of charge in one or more of the storage wells in each channel is sensed and employed in some cases for indicating the value of a bit of given significance, and in others for inhibiting or permitting the propagation of charge along a CCD channel employed to indicate the value of a bit of lower significance.

Abstract: A frequency synthesizer including a phase lock loop comprising a voltage controlled oscillator, a four phase modulator for modulating the oscillator output signal, a phase detector for comparing the phases of a reference signal and the output signal of the modulator and filter means for supplying the phase detector output signal back to the oscillator. The two most significant bits of an arithmetic synthesizer are supplied to the modulator to produce, in the absence of additional modulating signals, discrete increments of 90.degree. phase shift in the oscillator output signal. To eliminate phase jitter, the remaining lower order bit positions of the arithmetic synthesizer are converted to analog voltages which are supplied into the phase lock loop to effect a gradual phase shift between the otherwise discrete 90.degree. phase shifts. Continuous phase, constant amplitude output signal is thereby produced having a frequency translated by the phase shifts introduced by the arithmetic synthesizer.

Abstract: A digitized phase modulating system in which a clock pulse signal of frequency C.sub.a is divided by a counter of count capacity N, which when N=4, produces four signals having phases spaced at intervals of 0.degree., 90.degree., 180.degree. and 270.degree.. Signal selecting logic means including counting means is responsive to data clock pulses of frequency mf.sub.s (where m is an integer) and to the binary contents of successive states of a binary modulation sequence of bit rate f.sub.s to successively select various ones of said four signals whose successive phases are indicative of the contents of said successive states of said binary modulation sequence.

Abstract: A digitalized phase modulating means in which a two level binary modulated sequence from a data source of bit rate f.sub.s is supplied to a pulse add/delete circuit. Also supplied to such pulse add/delete circuit is a train of clock pulses of frequency C.sub.a, and a train of add/delete pulses having a repetition rate mkf.sub.s, where m and k are integers. The pulse add/delete circuit responds to a binary bit of value 1 or 0 to add or delete the said add/delete pulses to the train of clock pulses at a given rate, such as mk pulses per data bit period 1/f.sub.s. The altered clock pulse train is then supplied to a divider which divides by 4k to produce a cyclical output whose phase is advanced or retarded by 1/4k of 360.degree. each time a pulse is added or deleted from the clock pulse train C.sub.a.

Abstract: Method and circuit for controlling the color of dot elements in a raster scan display having a data memory for storing the state (on or off) of dot elements which are mapped onto the raster scan display and a smaller auxiliary memory for storing color information. The color information stored in a location of the auxiliary memory specifies the color of a plurality of contiguous dot elements so that the auxiliary memory can be much smaller than the data memory. The contiguous dot elements whose color is specified by a location in the auxiliary memory form a block which can be arranged so that the address bits to the auxiliary memory form a proper subset of the address bits to the data memory.

Abstract: A CCD structure which includes beneath a single electrode, in response to a voltage applied to that electrode, a first substrate region in which a potential barrier is formed, a second substrate region on one side of the first region in which a relatively shallow potential well is formed, and a third substrate region on the other side of the first region in which a deeper potential well is formed. This kind of structure is useful, for example, in obtaining multiplexed outputs from a CCD array.

Abstract: The present invention is applicable to a CCD imager of the field transfer type employing a single layer electrode structure comprising gate electrodes formed of semiconductor material of one conductivity type separated from one another by semiconductor material of opposite conductivity type. Sparkle is reduced by DC biasing the electrodes in the B register driven by at least one of the multiple phase voltages.

Abstract: The circuit includes means for limiting the potential difference that can exist between corresponding electrodes of two input transistors interconnected to form a differential amplifier stage. The control electrode of each input transistor is coupled via a normally conducting gating transistor to its respective input terminal and via a normally non-conducting clamping transistor to a common point to which is connected one end (source or emitter) of the main conduction paths of the two input transistors. In response to an input signal at an input terminal having a polarity and a first value to turn off an input transistor, the gating transistor is turned off and decouples the control electrode of the input transistor from its corresponding input terminal. Then, as the input signal increases beyond the first value in a direction to further reverse bias the input transistor, the clamping transistor is turned on and clamps the control electrode of the input transistor to the common point.

Abstract: A single crystal layer of either cadmium sulfide or an alloy of cadmium sulfide and indium phosphide is epitaxially deposited on a substrate of cadmium sulfide by liquid phase epitaxy using indium as the solvent.

Abstract: Amorphous silicon layers deposited on a suitable substrate in a glow discharge of silane or other silicon containing compounds are sensitive optical storage media.

Abstract: Apparatus and method for detecting the movement of a control device (such as a tuning knob) for controlling the input to a controlled device (such as a frequency synthesizer or display) operating in discrete or digital steps. The rotational direction of a single tuning device such as a "tuning" knob causes an increase or decrease of the frequency. The rate of movement of the positioning device determines frequency bandswitching in differing degrees of coarse to fine tuning modes. The utilization of rotational direction and rate of the device provides a single control for all tuning functions.The apparatus and method is useful in both open and closed (servo) loop systems.

Abstract: Circuit and method for synchronizing a clocked coded output signal with an iterative encoded input signal in a time relation that results in the greatest correlation. An AS (arithmetic synthesizer) initially produces a clock signal at a rate different from that of the input signal. The clock signal so produced drives a waveform generator that produces an iterative encoded signal similar in kind to the input signal. As the time (phase) relation between the generated signal and the input signal is varied, a correlation coefficient is derived at successive phase positions. The AS is then set into the condition of greatest correlation and synchronized with the input signal.

Abstract: A three-terminal current amplifier has a current gain substantially independent of the forward current gains of its component transistors. It employs a first transistor with collector-to-base feedback regulating its collector current flow to equal applied input current and a second transistor having a base emitter circuit in parallel with that of the first transistor. Output current from the collector electrode of the second transistor consequently is proportional to the input current. Means are provided for maintaining the collector potentials of the first and second transistors substantially equal to help maintain a fixed relationship between the output and input current amplitudes.