Abstract: Various embodiments of the present invention provide systems and methods for data equalization. For example, various embodiments of the present invention provide methods for generating equalization data. The method includes inputting N bits of an equalization data pattern into respective stages of a shift register, wherein inputting the N bits occurs synchronous to a system data clock having a system data rate, and shifting the N bits of equalization data to next adjacent next stages of the shift register synchronous to an equalization data clock having an equalization data rate N times the system data rate.

Abstract: Various embodiments of the present invention provide systems and methods for adaptive channel bit density estimation. For example, various embodiments of the present invention provide methods for adaptively estimating channel bit density. Such methods include providing a storage medium (178) that includes information corresponding to a process data set, and accessing the process data set from the storage medium (505). A first channel bit density estimate (535) is computed based at least in part on a first portion of the process data set (520-530), and a second channel bit density estimate (535) is calculated based at least in part on the first portion of the process data set, a second portion of the process data set (520-530) and the first channel bit density estimate (535).

Abstract: Various embodiments of a dimmable power supply are disclosed herein. For example, some embodiments provide a dimmable power supply including an output driver, a variable pulse generator and a load current detector. The output driver has a power input, a control input and a load path. The variable pulse generator includes a control input and a pulse output, with the pulse output connected to the output driver control input. The variable pulse generator is adapted to vary a pulse width at the pulse output based on a signal at the control input. The load current detector has an input connected to the output driver load path and an output connected to the variable pulse generator control input. The load current detector has a time constant adapted to substantially filter out a change in a load current at a frequency of pulses at the variable pulse generator pulse output.

Abstract: Systems and methods that can detect known undesired computer files in protected archives are provided. According to one embodiment, an archive file in transit across a network as an attachment to an email message destined for a client workstation is scanned, without decrypting or decompressing contents of the archive, by an anti-virus detection module running on a network gateway. A type and associated structure of the archive are identified by examining primary or secondary identification bytes of the archive. Based on the type and structure, descriptive information regarding a contained file is obtained. The descriptive information includes a hash value of the contained file in uncompressed format. If the descriptive information matches a signature of a known undesired computer file, then a clean version of the archive is produced by removing the contained file and regenerating the archive. Finally, the clean version of the archive is delivered.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

Abstract: Systems and methods for selective authorization of dependent code modules are provided. According to one embodiment, file system or operating system activity relating to a first code module is initiated by a running process associated with a second code module. The file system or operating system activity is intercepted by a kernel mode driver of a computer system. The kernel mode driver selectively authorizes loading of the first code module by the running process based at least in part on one or more attributes of the second code module.

Abstract: Various embodiments of the present invention provide systems and methods for data storage. As an example, storage devices are disclosed that include a plurality of memory blocks, an unreliable block identification circuit, and a partial failure indication circuit. Each of the plurality of memory blocks includes a plurality of memory cells that decrease in reliability over time as they are accessed. The unreliable block identification circuit is operable to determine that one or more of the plurality of memory blocks is unreliable, and the partial failure indication circuit is operable to disallow write access to the plurality of memory blocks upon determination that an insufficient number of the plurality of memory blocks remain reliable.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

Abstract: An apparatus to separate components of a solid feedstock is described. The apparatus may include a threaded shaft that has a plurality of reaction zone segments along the length of the shaft that are separated from each other by dynamic plug segments. The threads of the shaft have a first thread pitch in the reaction zone segments, and a second thread pitch in the dynamic plug segments. The apparatus may also include a motor to rotate the shaft, and an outlet coupled to a second end of the shaft, where one or more solid components of the solid feedstock exit the apparatus through the outlet. The apparatus may additionally include a feeder to supply the solid feedstock to the threaded shaft, and a pump to provide a rinse fluid to the threaded shaft, where the rinse fluid flows in the opposite direction of the solid feedstock along the shaft.

Abstract: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

Abstract: A mechanism is disclosed for enabling load balancing to be achieved in a loop-free switching path, reverse path learning network, such as an Ethernet network. The network is divided into a plurality of virtual networks, with each virtual network providing a different path through the network. When it comes time to send a set of information through the network, one of the plurality of virtual networks, and hence, one of the plurality of paths, is selected. The set of information is then updated to indicate the selected virtual network, and sent into the network to be transported along the selected path. With multiple paths, and with the ability to select between the multiple paths, it is possible to balance the load imposed on the multiple paths.

Abstract: A digital PFC (DPFC) control approach that requires no input voltage sensing or current loop compensation is described. The approach can provide stable, low-harmonic operation over a universal input voltage range and load ranging from high-load operation in continuous conduction mode down to near-zero load. A fast voltage loop can also be incorporated into a DPFC controller to provide additional control of the power stage. A controller can be based on low-resolution DPWM and A/D converters, can be implemented without microcontroller or DSP programming, and is well suited for simple, low-cost integrated-circuit realizations.

Abstract: Methods and systems for shielding layer two host addresses (e.g., MAC addresses) from a network are provided. According to one embodiment, a border component of a network of switches receives a first packet intended for a first host having a first L2 address and a first L3 address associated therewith. The first packet includes the first L3 address and a substitute L2 address as destination addresses. The substitute L2 address is associated with a communication channel of the border component. A data structure including information regarding an association between the first L3 address and the first L2 address is accessed by the border component. A determination is made that the destination L2 address for the first packet should be the first L2 address. A first updated packet is derived from the first packet by replacing the substitute L2 address with the first L2 address and sent to the first host.

Abstract: A method for transferring a nano material formed on a first substrate through deposition techniques to a second substrate, includes: (A) contacting the second substrate with a free end of the nano material on the first substrate; (B) heating the first substrate so that heat is conducted substantially from the first substrate through the nano material to the second substrate to soften a contact portion of a surface of the second substrate that is in contact with the free end of the nano material; (C) after step (B), cooling the second substrate so as to permit hardening of the contact portion of the surface of the second substrate and solid bonding of the nano material to the second substrate; and (D) after step (C), removing the first substrate from the nano material.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data receiving system is disclosed that includes a data signal provided from a medium that may include a defective portion. An absolute value circuit receives the data signal and provides an output corresponding to an absolute value of the data signal. The output corresponding to the absolute value of the data signal is input to a filter that filters it and provides a filtered output. In some cases, the filter is a digital filter operable to integrate the absolute value of the data signal. A comparator receives the output from the filter and compares it with a threshold value. The result of the comparison indicates a defect status of the medium.

Abstract: Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level.

Abstract: Methods and systems for creating three-dimensional models from two-dimensional images are provided. According to one embodiment, a computer-implemented method of creating a polygon-based three-dimensional (3D) model from a two-dimensional (2D) pixel-based image involves creating an inflatable polygon-based 3D image and extruding the inflatable polygon-based 3D image. The inflatable polygon-based 3D image is created based on a 2D pixel-based input image by representing pixels making up the 2D pixel-based input image as polygons. The inflatable polygon-based 3D image is extruded by generating z-coordinate values for reference points associated with the polygons based upon a biased diffusion process.