Abstract: A power supply includes a power source having at least one power source output, and a plurality of drivers connected to the at least one power source output. At least one of the plurality of drivers includes a bridge network having a first switch, a second switch and a bridge network output. The first switch is connected between the at least one power source output and the bridge network output. The second switch is connected between the bridge network output and a ground. The bridge network further includes at least one control input connected to the second switch. The bridge network is adapted to change a state of the first switch based on a state of the second switch.

Abstract: Methods and systems for creating three-dimensional models from two-dimensional images are provided. According to one embodiment, a method of creating an inflatable icon involves a vectorizing module polygonizing an input image to produce an inflatable image by representing a set of pixels making up the input image as polygons. The inflatable image is then extruded by an extrusion module by generating appropriate z-coordinate values for a reference point associated with each polygon of the inflatable image based upon a biased diffusion process. End-user controlled pressure modulation is supported by an interface module by (i) adjusting one or more modulation functions employed by the biased diffusion process based upon end-user input regarding relative modulation bias for a selected set of one or more pixels associated with the inflatable image or (ii) applying the biased diffusion process to only the selected set of one or more pixels.

Abstract: Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.

Abstract: A financial advisory system is provided. According to one aspect of the present invention, return scenarios for optimized portfolio allocations are simulated interactively to facilitate financial product selection. Return scenarios for each asset class of a plurality of asset classes are generated based upon estimated future scenarios of one or more economic factors. A mapping from each financial product of an available set of financial products onto one or more asset classes of the plurality of asset classes is created by determining exposures of the available set of financial products to each asset class of the plurality of asset classes. In this way, the expected returns and correlations of a plurality of financial products are generated and used to produce optimized portfolios of financial products. Return scenarios are simulated for one or more portfolios including combinations of financial products from the available set of financial products based upon the mapping.

Abstract: A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. In another implementation, a digital pulse-width-modulator with a digital phase-locked loop is also provided.

Abstract: Various embodiments of the present invention provide systems and methods for providing a corrected dibit signal. As an example, various embodiments of the present invention provide dibit correction circuits. Such dibit correction circuits include a dibit sample buffer, a maximum sample detector circuit, a side sample detector circuit, and a dibit correction circuit. The dibit sample buffer includes a plurality of samples of an uncorrected dibit signal. The maximum sample detector circuit identifies a maximum sample of the plurality of samples of the uncorrected dibit signal, and the side sample detector circuit identifies a first side sample prior to the maximum sample on the uncorrected dibit signal and a second side sample following the maximum sample on the uncorrected dibit signal.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: Systems and methods for tracking electronic messages and data are provided. In one embodiment, the invention consists of a method of tracking email messages. In various embodiments, steps may include a) identifying an email message for tracking and b) inserting a linking object, into a tracked email message. Responsive to activation by a receiver of the email message, the linking object enables the receiver to submit information to a commercial anti-spam service or a commercial anti-virus service. The method can be used to identify and track email messages defined as spam or defined as containing viruses. The receiver's privacy may be preserved with respect to content of the email message by limiting the information submitted to signatures of the electronic message and other information associated with the electronic message that are reasonably required for spam or virus analysis.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: Firewalls and other filtering gateways have become common security devices for improving computer network security. As more features and functionality are added to these devices they become quite complex to configure. By associating configuration schemes with firewall policies, configuration can be simplified without compromising flexibility. Administrators have more options to filter different traffic streams based on their type and sources. They also have increased flexibility to be able to filter traffic on a per user basis, through authentication mechanisms tied to various filtering options.

Abstract: Methods are provided for managing hierarchically organized subscriber profiles. According to one embodiment of the present invention, a subscriber connection is created with a virtual router operable within a telecommunications system of a service provider. A connection request is received from a subscriber of multiple subscribers of the service provider at a subscriber manager of the virtual router. The virtual router maintains a database of hierarchically organized profile identifiers, including multiple lower-level profile identifiers, which explicitly define subscriber services, and multiple first-level profile identifiers, which define service contexts representing combinations of services available to subscribers when connected by (i) explicitly defining the subscriber services or (ii) referring to one or more of the multiple lower-level profile identifiers.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase.

Abstract: A mechanism is disclosed that enables layer two host addresses (e.g. a MAC addresses) to be shielded from a network. In one implementation, the mechanism updates each packet sent by the hosts into the network to indicate that the source layer two (L2) address for that packet is a shared L2 address instead of the actual L2 address of the sending host. By doing so, the mechanism exposes only the shared L2 address to the network, and shields the actual L2 addresses of the hosts from the network. The effect of this is that the switches in the network will need to store only the shared L2 address in their forwarding tables, not the actual L2 addresses of the hosts. By reducing the number of L2 addresses that need to be stored in the forwarding tables of the switches, the mechanism improves the scalability of the network.

Abstract: Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output.

Abstract: Methods and systems for bridging Ethernet frames transmitted over heterogeneous media channels are provided. According to one embodiment, multiple Ethernet frames encapsulated within multiple in-bound media transmissions having different media formats are received via a first set of multiple network interfaces of a network-computing device. The multiple in-bound media transmissions are relayed via a switch fabric of the network-computing device to a virtual bridge application running on a processing resource shared by the network interfaces and which acts as a single bridging domain for all Ethernet frames. The virtual bridge application encapsulates the multiple Ethernet frames within multiple out-bound media transmissions by performing media agnostic Ethernet bridging of the multiple Ethernet frames. The multiple Ethernet frames are transmitted by relaying, via the switch fabric, the out-bound media transmissions to a second set of the multiple network interfaces.

Abstract: Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.

Abstract: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds.

Abstract: Various embodiments of the present invention provide systems and methods for performing data equalization. For example, various embodiments of the present invention provide data equalization circuits that include an equalization circuit and a transition adjustment circuit. The equalization circuit receives a series of at least two original data bits and replaces at least one of the two original data bits with an equalization pattern including two or more equalization bits. The original data bits correspond to an original data clock, and the two or more equalization bits correspond to an equalization data clock. The transition adjustment circuit is operable to modify an occurrence of a transition from one logic state to another logic state within the equalization pattern on a sub-equalization data clock basis.