Abstract: A lateral bipolar transistor and method of making which is compatible with making BICMOS circuits are disclosed. The method includes: Forming on a substrate of one conductivity type at least one layer of a semiconductor material of opposite conductivity type. Forming a first region of opposite conductivity type into one portion of the layer and a highly conductive contact region to the layer in another portion, forming a layer of an insulating material over the layer and providing an aperture therethrough to the first region. Depositing a layer of polycrystalline silicon over the insulating layer and in the aperture so that it is in the aperture and extends a short distance beyond the aperture but not beyond the edge of the first region.

Abstract: A method of fabricating a semiconductor structure, comprising the steps of: providing a monocrystalline semiconductor device region of a first conductivity type; forming a layer of intrinsic monocrystalline semiconductor material over the device region; forming a layer of insulating material over the layer of intrinsic monocrystalline semiconductor material; forming a conductive contact over a portion of the layer of insulating material; forming an aperture extending through the conductive contact, and the layers of insulating material and intrinsic monocrystalline semiconductor material to define an aperture exposing a selected portion of the layer of intrinsic monocrystalline semiconductor material; and forming a layer of semiconductor material of a second conductivity type including a monocrystalline portion disposed epitaxially over the device region portion and a polycrystalline portion extending onto the wall of the conductive contact within the aperture.

Abstract: An apparatus and method for determining the time at which a plasma etching process should be terminated. The process generates at least one etch product species and a continuum plasma emission. The apparatus monitors the optical emission intensity of the plasma in a narrow band centered about a predetermined spectral line and generates a first signal indicative of the spectral intensity of the etch product species. The apparatus further monitors the optical emission intensity of the plasma in a wide band and generates a second signal indicative of the spectral intensity of the continuum plasma emission. The apparatus further monitors the magnitudes of the first and second signals and generates a termination signal when the magnitudes diverge.

Abstract: A reusable isolation enclosure has a closure member adapted for purging gases from the enclosure. The closure member includes filters and vapor and moisture drains. Replacement of ambient environmental gases in the sealed enclosure is provided. A purge gas is provided by the gas replacement system which quickly connects to the enclosure and quickly disconnects from the enclosure. Suction cups surrounding the ends of gas connection lines form the interface to the filter membrane and form a sealed connection with the closure member. No other mechanical connection than the suction cups is required. The outlets and inlets of the purging system and the exhausting system are automatically disconnected by a spring valve when the isolation container to be purged is removed. When the closure member of the isolation enclosure is placed upon the purge system the weight of the package compresses the valve spring opening the valves, permitting the purge gas to flow.

Abstract: A reusable isolation structure features an easily cleanable shell. The opening of the shell includes a groove formed around the periphery thereof and is preferably not more than slightly smaller than an interior cross-section of the shell. A closure member (door) of the isolation structure is dimensioned to fit within the opening and has a resilient seal member clamped to the periphery of a backbone by front and rear plates. The front and rear plates cooperate with grooves formed in the backbone to define a preferred form of manifold for coupling pressure or a vacuum to the interior of the resilient seal member whereby the resilient seal member may be collapsed to allow removal of the closure member or allowed to expand or pressurized to provide secure closure member. A vacuum structure for handling the closure member simultaneously provides for evacuation and controlled collapse of the resilient seal member as well as containment of contamination of the exterior thereof.

Abstract: An Algorithmic Test Pattern Generator (APG) of sufficient simplicity to be replicated at every pin of a tester. This APG is comprised of two counters and various controls capable of manipulating the counters and generating output data which is based on command and counter status. The circuit is capable of testing VLSI logic and analog circuitry, and is specifically well suited to test embedded arrays that can only be accessed through LSSD shift register chains.

Abstract: A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.

Abstract: A CHF.sub.3 -based RIE etching process is disclosed using a nitrogen additive to provide high selectivity of SiO.sub.2 or PSG to Al.sub.2 O.sub.3, low chamfering of a photoresist mask, and low RIE lag. The process uses a pressure in the range of about 200-1,000 mTorr, and an appropriate RF bias power, selected based on the size of the substrate being etched. The substrate mounting pedestal is preferably maintained at a temperature of about 0.degree. C. Nitrogen can be provided from a nitrogen-containing molecule, or as N.sub.2. He gas can be added to the gas mixture to enhance the RIE lag-reducing effect of the nitrogen.

Abstract: A process, compatible with bipolar and CMOS silicon device manufacturing for fabricating complementary buried doped regions in a silicon substrate. An N+ doped region (12) is formed in the silicon substrate by known methods of arsenic doping and drive in. This is followed by depositing a first thin epitaxial silicon cap layer (14), under conditions of minimum N+ autodoping. Part thickness of this first epilayer is converted to oxide (18), and the oxide is patterned to provide apertures in an area where it is desired to form a P+ region. A P source material (20) is deposited and a drive in anneal is used to dope the silicon with P in the areas of the oxide aperture opening. Subsequent to drive in, the dopant source layer and the oxide mask is removed by wet etching. An oxide is regrown on the surface, including the P+ region (22), and subsequently the oxide layer is stripped in dilute hydrofluoric acid.

Abstract: There is disclosed a high density electronic connector system in which a plastic insulating body supports on one or more levels a plurality of conductive circuit traces. Output contacts to these traces are provided by small metal balls. The metal balls are driven into tight contact with respective ones of the conductive traces and captivated by the plastic body. The balls are covered with gold and provide miniature, wear resistant closely spaced output contacts in the connector system. A ball may contact conductive traces on two levels of the insulating body and thereby provide an electrical connection between conductive traces. A method of manufacture of the connector system includes the steps of heating the plastic body to an elevated temperature, and driving the small metal balls through or against a respective conductive trace and into the plastic body which thereby captivates it. The conductive traces may be solder plated.

Abstract: A reusable isolation structure features an easily cleanable shell having viewing windows formed therein, each protected by a framing ridge or a recess integrally formed in the shell provides protection of contents from contamination, impact, vibration and tampering. Framing ridges or recesses also facilitate stacking of shells. The closure member opening of the shell includes a groove formed around the periphery thereof and is preferably not more than slightly smaller than an interior cross-section of the shell. A door of the isolation structure is dimensioned to fit within the closure member opening and has a resilient seal clamped to the periphery of a backbone by front and rear plates. The front and rear plates cooperate with grooves formed in the backbone to define a preferred form of manifold for coupling pressure or a vacuum to the interior of the resilient seal whereby the resilient seal may be collapsed to allow removal of the door or allowed to expand or pressurized to provide secure closure.

Abstract: A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.

Abstract: A method and apparatus for producing a laser diode assembly package is taught. Briefly stated, in a first embodiment, a housing having an access area at one end has a laser mounted therein. A collimator lens is placed at the other end of the housing and is movable along the optical axis of the laser output. This enables the collimator to be adjusted along the optical axis in order to produce an optimum amount of collimated light, with the housing and lens then be hermetically sealed with UV curable epoxy. In an alternate embodiment, the laser is mounted on a socket module which is then inserted into the housing.

Abstract: Etching processes are disclosed for producing a graded or stepped edge profile in a contact pad formed between a chip passivating layer and a solder bump. The stepped edge profile reduces edge stress that tends to cause cracking in the underlying passivating layer. The pad comprises a bottom layer of chromium, a top layer of copper and an intermediate layer of phased chromium-copper. An intermetallic layer of CuSn forms if and when the solder is reflowed, in accordance with certain disclosed variations of the process. In all the variations, the solder is used as an etching mask in combination with several different etching techniques including electroetching, wet etching, anisotropic dry etching and ion beam etching.

Abstract: An improved metal mask-making process is disclosed which involves starting with a metal mask having etched apertures using existing processes and coating it conformably with a substantially thick layer, so as to reduce the minimum aperture size while increasing the metal mask thickness. The conformal layer is chosen for minimum stress, good adhesion and thermal compatibility to the original metal mask material. Additional thin conformal coatings can be provided for imparting mechanical and chemical resistance to the metal mask.

Abstract: A wafer polishing fixture is disclosed containing a first liquid film confined by a non-porous but flexible enclosure for distributing evenly the applied polishing forces across the surface of a wafer supported by the confined liquid. The fixture comprises a flexible, non-porous template with a pocket for receiving a wafer to be polished. A washer is placed between a carrier and the template pocket. A film of water fills the bottom of the pocket and is confined with the aid of the washer and by an overlying porous pad extending across the pocket and having a non-porous sheath facing the liquid. A second liquid film saturates and covers the upper surface of the pad. The wafer to be polished floats upon the second liquid film within the pocket.

Abstract: A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.

Abstract: A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.