Abstract: A process for making local interconnection of devices on a semiconductor substrate is disclosed. Contact openings are defined to a plurality of devices on the substrate. A blanket layer of germanium is deposited over the substrate, followed by deposition of a blanket layer of electrically conducting material on top of the germanium layer. The conducting layer is etched first stopping at the germanium layer. Subsequently the germanium layer is etched by a different process, selective to the conductive layer and the device contact. The conducting layer is preferably one of the following materials: polysilicon, silicide, a composite of polysilicon with metal or silicide films.

Abstract: A method and apparatus for the inspection and handling of surface level defects is taught. Briefly stated, the object to be inspected is positioned. A Laser light is polarized into at least one orientation and then reflected off of a rotated polygon mirror. This causes the light to "move" over the area of interest. A plurality of fiber optic bundles are used to receive and conduct the reflected light back to photomultipliers. The photomultipliers convert the light into electrical signals while associated electronics digitize the signals, keeping track of pixels which are produced. By keeping track of pixel edge boundaries and determining if certain thresholds are exceeded or not met as appropriate, the area of interest can be checked for a variety of defects. By comparison of the defects to a reference base, the defects and hence the items inspected can be categorized.

Abstract: A method and apparatus for the inspection and handling of surface level defects is taught. Briefly stated, the object to be inspected is positioned. A Laser light is polarized into at least one orientation and then reflected off of a rotated polygon mirror. This causes the light to "move" over the area of interest. A plurality of fiber optic bundles are used to receive and conduct the reflected light back to photomultipliers. The photomultiplers convert the light into electrical signals while associated electronics digitize the signals, keeping track of pixels which are produced. By keeping track of pixel edge boundaries and determining if certain thresholds are exceeded or not met as appropriate, the area of interest can be checked for a variety of defects. By comparison of the defects to a reference base, the defects and hence the items inspected can be categorized.

Abstract: A tri-state circuit is provided having first and second input lines for each receiving an input signal thereon. A circuit output line is connected to and controlled by an output switching circuit. A control circuit is responsive to both input signals to cause the switching circuit to adopt one of three states wherein the switching circuit delivers a high logic signal to the output line in a first state, a low logic signal in a second state, and no output signal in a third state. The circuit includes circuitry connected to the switching circuit and the output line for reducing the current in the output line to substantially zero over a transient period when the switching circuit is in the third state. The control circuit further includes a delay circuit for substantially reducing the transient period thereby minimizing the amount of current flowing in the output line when the circuit is in the third state.

Abstract: There is disclosed a high density electronic connector system in which a plastic insulating body supports on one or more levels a plurality of conductive circuit traces. Output contacts to these traces are provided by small metal balls. The metal balls are driven into tight contact with respective ones of the conductive traces and captivated by the plastic body. The balls are covered with gold and provide miniature, wear resistant closely spaced output contacts in the connector system.

Abstract: A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal.

Abstract: A method of forming a semiconductor structure comprising the steps of: providing a body of semiconductor material including at least one generally planar surface; forming a mesa having at least one generally vertical wall over the planar surface; forming a layer of material generally conformally over the mesa and the planar surface so as to form a vertical spacer on the vertical wall; forming a protective mask selectively on the upper portion of the vertical spacer; and using the protective mask to etch and remove the unmasked portions of the layer of material and the mesa while leaving the vertical spacer.The process is used to form an FET by forming a gate insulating layer underneath of the vertical spacer, the vertical spacer being selected to comprise a conductive gate material such as doped polysilicon. The vertical gate structure is then used as a mask to dope the source and drain regions.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: A low copper concentration multilayered, device interconnect metallurgy, comprises an aluminum-copper (<2 weight percent copper) conductor having formed on one of its surfaces a layer of an intermetallic compound formed from a Group IVA metal and aluminum from the aluminum-copper conductor. The intermetallic compound is formed so as to contain only the single phase line compound of the intermetallic compound.

Abstract: A flexible capacitor (1) includes a dielectric made of flexible material, coated on each side with conductive material for insertion between a cable shield being at the ground potential of a remote electrical machine, and a part on a local machine being at the local ground potential (3, 5, 2) for example at a connector (7) level.

Abstract: An electrostatic chuck includes a body of refractory metal, preferably molybdenum, sized to support a semiconductor wafer. A first layer of diamond having a thickness in the range of 0.1-5.0 microns coats the refractory metal body. A pair of generally planar electrodes, preferably formed by molybdenum, are disposed on the first layer of diamond. A second layer of diamond, of like thickness as the first layer, conformally coats the pair of electrodes. A dc voltage applied across the pair of electrodes develops an electrostatic force to hold the wafer against the second diamond layer.

Abstract: A method for locating electrical short circuits in an electronic substrate containing a plurality of conductive paths. A pair of shorted paths is identified and a current signal is applied thereto. Simultaneously, the voltage across the shorted paths is measured. The current signal is then increased in incremental steps until the voltage starts to vary nonlinearly with respect to the current signal. A temperature differential is then created between the substrate as a whole and small sectors of the substrate until the measured nonlinear relationship between current and voltage reverses in the direction of resuming a linear relationship. The small sector which caused the voltage to respond to the temperature differential is then identified, thereby identifying the approximate location of the short circuit.

Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.

Abstract: A temperature sensor, comprising: a diode structure including, a) a silicon substrate, b) a first region of a metal silicide in the silicon substrate, c) a second region of a metal-oxide semiconductor material on the first region, d) a third region of a metal over the second region; and, means for using the diode structure as a temperature sensitive device to measure an ambient temperature. The metal-oxide semiconductor material is preferably selected to have a bandgap of not less than about 3.0 eV.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: A method and apparatus for determining the thickness of an interfacial oxide film intermediate to a polysilicon layer of a first conductivity type and a silicon substrate of a second conductivity type supporting a p-n junction. Radiant energy, preferably in the form of light, is directed on to the top surface of the polysilicon layer thereby stimulating carriers which concentrate at the interfacial oxide film, allowing the excited carriers to diffuse across the oxide film, and creating a short circuit, the magnitude of which is inversely related to the thickness of the interfacial oxide film.

Abstract: Accordingly, an apparatus has been provided for printing identifying indicia on a work product. The apparatus includes a print mechanism and a transport for imparting relative motion between the work product and the print mechanism. The work product and the print mechanism are positioned in close proximity to one another. A control is provided for causing the print mechanism to print predetermined identifying information on the work product when the work product and the print mechanism reach a desired location as they move with respect to each other. In the preferred embodiment the print mechanism has a fixed print electrode with a moving resistive ribbon associated therewith. A track is provided for supporting the work product on air bearings. A moving vacuum belt moves the work product along the track and thereby moves the work product with respect to both the print electrode and the ribbon.

Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.

Abstract: A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to de

Abstract: A method of forming a bipolar transistor is provided, comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming a layer of insulative material over a surface of the first region; forming a layer of conductive material over the layer of insulative material; patterning the first and second layers to form a generally vertical sidewall bounding an exposed portion of the first region surface; and epitaxially depositing a base region of a second conductivity type over the exposed portion of the first region surface and the sidewall such that the base region is in electrical contact with the second region.