Abstract: A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.

Abstract: An integrated automatic bus setting, sensing and switching interface unit is manufactured on board an integrated circuit to interface between the integrated circuit and the system bus. The interface unit can support a plurality of bus structures utilizing the same pins on the integrated circuit for different functions. Several modes of establishing an interface structure are available in the unit. An Address Strobe pin on the integrated circuit is used to automatically detect a signal level representative of the bus structure to be used. A code representative of the parameters of the bus structure is also stored in a configuration register for controlling the interface unit and configuring the pins on the integrated circuit for the specific bus structure to be used. The Basic Input Output System (BIOS) as its first operation stores the code in a register whose contents are then written to the configuration register of the integrated circuit for controlling and configuring the integrated circuit.

Abstract: A generally cylindrical shaped tool handle holds multiple sizes of tools. The preferred embodiment of the handle is hexagonal shaped and holds multiple sizes of hexagonal tools. The handle includes one or more holding slots each positioned on one of multiple surface faces into which hexagonal tools are inserted and held. Each holding slot is of a size and dimension which corresponds to a hexagonal tool size. In use, a hexagonal wrench is positioned in the appropriate holding slot with the short leg or mounting end of the hexagonal wrench resting in the holding slot and the long leg of the hexagonal wrench extending through a receiving hole formed through the bottom of the slot and the tool handle. The long leg having a proximal end for driving the screw or tool. A lock is then positioned over the short leg of the hexagonal wrench and the holding slot.

Abstract: An oscillator for generating a varying amplitude feed forward power factor correction (PFC) modulation ramp signal includes a clock generating circuit and a ramp generating circuit. The PFC ramp signal generated by the ramp generating circuit is used within a power factor correction circuit of a switching mode power converter. The timing capacitor used within the ramp generating circuit is charged from the full wave rectified line input voltage so that the amplitude of the generated ramp output signal will follow the full wave rectified input signal, thereby maintaining the current loop bandwidth at a constant value and improving the transient response of the circuit. A one-shot circuit is coupled between the discharge transistor of the clock generating circuit and the discharge transistor of the ramp generating circuit for synchronizing the clock and ramp reference signals generated by the oscillator so that the frequency of the ramp reference signal is equal to the frequency of the clock signal.

Abstract: The present invention relates to an improved apparatus and screwless method for rack mounting an independent rail to a peripheral electronic component or primary rail. First, a spring-urged elongated arch having a convex surface and a concave surface is engaged by depressing the convex surface, the arch further having an engaged state and disengaged state, two legs, each of the legs being placed at an opposite end of the concave surface and angled inward of the arch. Second, the two legs are individually directed through two apertures in the independent rail. Third, the two legs are subsequently directed into two apertures in the peripheral electronic component. Finally, when the convex surface is released, the two legs retract and clamp the peripheral electronic component within the apertures of the peripheral electronic component.

Abstract: An amplitude error detection and correction circuit apparatus and method can be used to detect and correct errors in signal amplitudes of a low information content signal during playback or transmission. The difference values dS/dt between the amplitudes of each sample and its neighboring samples are analyzed and compared to a maximum difference value dS.sub.max /dt. If the difference values dS/dt for a sample exceed the maximum difference value dS.sub.max /dt then the sample amplitude is elided or adjusted during playback or transmission to minimize distortion within the signal. The maximum difference value dS.sub.max /dt is determined by either the known characteristics of the signal type, analyzing a predetermined number of samples around the sample or grouping the data as it is input and storing or transmitting a maximum difference value for each group. The signal can be analyzed during the input of the signal, if the signal is accessible at this time, and the maximum difference value dS.sub.

Abstract: An electronic instrument that records electric power measurements. The instrument contains two types of memories: the first type of memory can tolerate wide fluctuations in ambient temperature but is expensive per unit of storage capacity, and the second type of memory only operates in a narrow ambient temperature range but is inexpensive per unit of storage capacity. For example, the two types of memory may be static Random Access Memory (RAM) and a hard disk drive, respectively. The instrument contains more storage capacity of the second type than storage capacity of the first type. The instrument records all of its measurements in the first type of memory. It also monitors the ambient temperature. When it detects an ambient temperature that will permit the second type of memory to function properly, it flushes the first type of memory into the second type of memory, thus creating space for recording subsequent data in the first type of memory.

Abstract: A voicemail message processing system. A voicemail message is sent to a remote recipient on a remote voicemail system. In response, the remote voicemail system sends an acknowledgment message containing information on the remote voicemail user. This information is stored for later use in addressing messages to the remote user, such as providing voice confirmations and address by name capabilities.

Abstract: A synchronous switching cascade connected power converter includes a first power factor correction converter stage and a second DC to DC converter stage for generating an output voltage in response to an input voltage and current. The output voltage is controlled by a circuit which measures a level of current within the circuit, compares that level to a predetermined desired level, and develops a response elsewhere in the circuit. Leading edge modulation for the first stage and trailing edge modulation for the second stage is implemented to realize synchronous switching between the two power stages. A single reference clock signal is used to control both the power stages. The duty cycle of the first stage is varied according to the input voltage. The duty cycle of the second stage is ideally held constant at fifty percent but will vary as the input voltage to this stage varies.

Abstract: A diffuse infrared communication link provides for communication directly between nodes each having a transceiver. A repeater may be present to facilitate communication. Each node is automatically reconfigurable between operation with or without a repeater. When a repeater is present each node automatically ignores any transmission by another node.

Abstract: A more efficient driver circuit for a power output stage, comprising a power driver stage activating the power output stage; a trigger circuit having an input stage and activating the power driver stage; and a power supply stage, wherein the input stage comprises a means for the potential-separated feeding of input signals, and the power supply stage comprises a means for the potential-separated feeding of electrical power. Such a driver circuit allows short signal propagation delays, is compact and small in size and has a wide clock frequency bandwidth.

Abstract: A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation, and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. This 20MHz 6th order Bessel filter and 2nd order equalizer operate from 5V, and generate only 0.24% (-52dB) of total harmonic distortion when processing 2Vp-p differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36Mbps, and is built in a 1.5 .mu./4GHz BiCMOS technology.

Abstract: In a computer network having a plurality of interconnected terminals and a shared memory device for storing digital data, a message handling system for sending and retrieving both voice and text messages over the computer network. A voice message is input either through a phone associated with one of the computer terminals or via a remote phone. The voice message is converted into a digital voice file which is stored on the shared memory device corresponding to the intended recipient's mailbox. Thereby, one mailbox can contain both voice and text messages. The same message handling mechanism is used for handling both voice and text messages. A list of the messages currently stored for each mailbox can be pulled for display by their respective terminals. A selected voice message may be selected for playback over the phone. Likewise, a text message may be selected for display by the terminal. Call answering and remote playback functions are also provided.

Abstract: A vertically stacked planarization machine includes two or more vertically stacked individual platens on which wafers are polished. The wafers are held by wafer holders which may rotate the wafers. The individual platens are also orbited in order to polish the wafers. The platens may have a top and bottom polishing pad for polishing multiple wafers. A single wafer holder, using hydraulic or pneumatic means, between two platens will hold and exert pressure on both a downward wafer and an upward wafer. The pressure exerted onto the top and bottom wafers by the dual wafer holder is designed to be equal to prevent any bowing of the platen. The platens are supported by three vertical members positioned at 120 degree intervals around the circumference of the platens to form a platen stack. Transport elevators are used to carry the wafers to and from the wafer holders and the platens.

Abstract: According to the present invention, a PLL circuit is designed to include an active mode, a sleep mode and an idle mode. In the idle mode, the PLL draws substantially less power than that in the active mode. In order to return to the designed operating frequency immediately, the PLL periodically refreshes itself in this mode of operation. The power consumption of the PLL is dependent upon the ratio of on-time to off-time which is a fraction of the power consumed in the active mode. Preferably, the PLL is designed to receive an external clock signal as a reference clock from which it develops the internal system clock. The PLL also receives a lower frequency refresh signal for activating a refresh operation during the idle mode. The PLL can power itself down after completing a single phase compare operation. The refresh signal which can be derived from a real time clock must be synchronized to the external reference clock. Thus, the PLL includes a zero-phase-restart circuit.

Abstract: The invention is an active, hot insertable, SCSI terminator circuit having a bypass device that permits an initially unpowered active SCSI terminator to be coupled to a signal line of a powered SCSI bus such that no damage results to the SCSI terminator circuit itself or to other SCSI devices on the SCSI bus, and without having the effect of altering the existing state of the SCSI bus as a result of the coupling. Preferably, the terminating element of the SCSI terminator is a p-channel MOSFET. The SCSI terminator is prevented from being damaged during the coupling by using the bypass device to effectively short the gate of the p-channel MOSFET terminating element to its drain. When the drain of the p-channel MOSFET terminating element is shorted to its gate the amount of current the SCSI terminator may draw from any and all SCSI signal lines during the coupling is substantially limited to less than 50 .mu.A.

Abstract: A system transfers electric power between two devices using a magnetic coupling and no electrical connections. Each device incorporates a magnetic core surrounded by a coil. When properly aligned the cores form a closed magnetic circuit whereby stray magnetic fluxes are substantially reduced. In the preferred embodiment, a base unit incorporates a substantially `C` shaped magnetic core surrounded by its respective coil. A portable detachable device, such as an electric toothbrush, incorporates a substantially linear shaped magnetic core surrounded by its coil. The linear shaped magnetic core and the portable device are configured to fit within a gap formed in the `C` shaped magnetic core forming a substantially closed magnetic circuit thereby. Stray magnetic fluxes are thus significantly reduced. Additionally, an apparatus deactivates the power to the coil in the base unit when the portable device is removed from the base unit or when the battery within the portable device is charged to a predetermined level.

Abstract: An adaptive lossless data compression system with systolic string matching logic performs compression and decompression at the maximum rate of one symbol per clock cycle. The adaptive data compression system uses an improvement of the LZ1 algorithm. A content addressable memory (CAM) is used to store the last n input symbols. The CAM is stationary, stored data is not shifted throughout the CAM, but rather the CAM is used as a circular queue controlled by a Write Address Pointer Counter (WREN). During a compression operation, a new input symbol may be written to the CAM on each clock cycle, while simultaneously the rest of the CAM is searched for the input symbol. Associated with each word of the CAM array is a String Match State Machine (SMSM) and, an address logic module (ALM). These modules detect the occurrence of strings stored in the CAM array that match the current input string and report the address of the longest matching string nearest to the Write Address Pointer.

Abstract: The present invention is for an active rectifier for use in a DC to DC converter wherein a feedback control circuit activates and de-activates the current conduction between the input and the output. Preferably, the current conductor between the input and the output is a P-type MOSFET, wherein the feedback control circuitry provides the activation or de-activation signal to the gate of this transistor. The feedback control circuitry provides an activation signal to the transistor when the input voltage is greater than the output voltage, and provides a de-activation signal to the transistor when the input voltage is equal to or less than the output voltage. Because the P-MOS rectifier has a lower voltage drop than the Schottky diode, the forward drop is reduced. In addition, the feedback control circuit is designed to draw no current except when the P-MOS rectifier is conducting.

Abstract: A low power clocking circuit includes a crystal oscillator for generating a digital signal having a first frequency. The first frequency is relatively slow which allows the crystal oscillator to consume reduced power. The phase detector signal is coupled to control a charge pump circuit that generates a voltage on an output node for controlling a voltage controlled oscillator. The VCO generates a clock signal having a second frequency that is higher than the first frequency. The charge pump circuit includes an active mode and a power down mode and is operatively coupled between a first supply voltage and a second supply voltage. As typically provided, the charge pump includes a capacitor network coupled to the output node for maintaining the output voltage. The charge pump includes a voltage control circuit having an up input for increasing the output voltage and a down input for decreasing the output voltage.