Patents Represented by Attorney, Agent or Law Firm Haynes and Boone LLP
  • Patent number: 8349680
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Yu Chao Lin
  • Patent number: 8349739
    Abstract: The present disclosure provides a method for etching a substrate. The method includes forming a resist pattern on the substrate; applying an etching chemical fluid to the substrate, wherein the etching chemical fluid includes a diffusion control material; removing the etching chemical fluid; and removing the resist pattern.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Patent number: 8350586
    Abstract: Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ying Cho, Jiun-Kai Huang, Wen-Sheh Huang, Sally Liu
  • Patent number: 8353026
    Abstract: A credential caching system includes receiving a set of authentication credentials, storing the set of authentication credentials in a credential cache memory, wherein the credential cache memory is coupled with a management controller, and supplying the set of authentication credentials for automatic authentication during a reset or reboot. In the event of a security breach, the credential caching system clears the set of authentication credentials from the credential cache memory so that the set of authentication credentials may no longer be used for a reset or reboot.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: January 8, 2013
    Assignee: Dell Products L.P.
    Inventors: Muhammed K. Jaber, Mukund P. Khatri, Kevin T. Marks, Don Charles McCall
  • Patent number: 8351287
    Abstract: Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Lattice Semiconductor Corporation
    Inventors: Rohith Sood, Fabiano Fontana, Zheng Chen
  • Patent number: 8351028
    Abstract: According to an embodiment, a measuring device for measuring a laser beam comprises a magnification lens system with a total of two lenses which are arranged in series in the beam path of the laser beam and whose foci are coinciding, as well as a camera which is arranged behind the two lenses in the focus of the last lens and includes an electronic image sensor which generates an electronic image of the magnified laser beam. The lenses together with the camera are adjustable along the beam path relative to a reference point of the measuring device, for the purpose of locating the beam waist of the laser beam and of determining a diameter profile of the laser beam. The measuring device further comprises an adapter enclosing the beam path for coupling the measuring device to a laser system which provides the laser beam.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: January 8, 2013
    Assignee: Wavelight GmbH
    Inventors: Bernd Zerl, Olaf Kittelmann
  • Patent number: 8352325
    Abstract: A method, system and computer program product for conducting an online auction of a plurality of heterogeneous items between a plurality of selling and potential purchasing parties. The method includes the steps of accepting an offer in respect of an item, accepting one or more subsequent offers that is/are preferable to a previously accepted offer, and rejecting the previously accepted offer. While the offer/s is/are binding on a party making the offer, acceptance of the offer/s is/are not binding on a party accepting the offer. Classes of “seller strategies”, for offering items to potential purchasing parties, and “buyer strategies”, to decide which offers to accept, are also disclosed. As a result of the interaction of the buyer and seller strategies, the auction mechanism converges to an allocation of items to buyers at particular prices and assists in discovering a free and fair competitive equilibrium price.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: January 8, 2013
    Assignee: Ebay Inc.
    Inventors: Rahul Garg, Debasis Mishra
  • Patent number: 8352888
    Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
  • Patent number: 8349628
    Abstract: An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: January 8, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Yung-Chang Chen, Hsin-Hsien Wu, Chyi Shyuan Chern, Ching-Wen Hsiao, Fu-Wen Liu, Kuang-Huan Hsu
  • Patent number: 8350327
    Abstract: A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Wei Vanessa Chung, Kuo-Feng Yu
  • Patent number: 8351578
    Abstract: A wiring verification system is disclosed for testing the correct pairing of a plurality of subscriber lines between an existing line termination system and a replacement line termination system to assist in the transfer of the subscriber line terminations from the existing line termination system to the replacement system. The wiring verification system comprising a controller and two testheads, one of which places test calls from the line under test to a designated test line that is terminated by the second testhead. The electrical qualities of the wye splices between lines associated with new line termination system and those of the existing line termination system are analyzed for correctness and possible hazardous conditions. The directory number of the line under test can be verified by decoding the calling line ID. Automated test strategies provide details related to which splices require attention and suggestions for remediation.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 8, 2013
    Assignee: Genband US LLC
    Inventor: Joseph Marcus Elder
  • Patent number: 8352062
    Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Jen Wu, Chen-Ming Huang, An-Chun Tu
  • Patent number: 8349477
    Abstract: A leak detection sensor for detecting a leakage of an electrolyte solution in a flow battery system is provided. The sensor includes a sensor housing, the sensor housing being at least partially surrounded by a fluid and having mounted therein at least one light source.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: January 8, 2013
    Assignee: Deeya Energy, Inc.
    Inventors: Gopalakrishnan R. Parakulam, Saroj Kumar Sahu, Rick Winter
  • Patent number: 8347720
    Abstract: A tunneling accelerometer includes a proof mass that moves laterally with respect to a cap wafer. Either the proof mass or the cap wafer includes a plurality of tunneling tips such that the remaining one of proof mass and the cap wafer includes a corresponding plurality of counter electrodes. The tunneling current flowing between the tunneling tips and the counter electrodes will thus vary as the proof mass laterally displaces in response to an applied acceleration.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: January 8, 2013
    Assignee: Tialinx, Inc.
    Inventors: Hector J. De Los Santos, Farrokh Mohamadi
  • Patent number: 8348166
    Abstract: System and method for surveying. In one embodiment, a process is provided including detecting a barcode associated with a position of interest. The barcode may be decoded to extract data associated with the position of interest. Additionally, decoded data associated with the position of interest can be presented to an operator of a surveying tool.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: January 8, 2013
    Assignee: Trimble Navigation Limited
    Inventor: Nigel Peter Hanson
  • Patent number: 8345536
    Abstract: A distributed-forwarding router platform contains a master and a standby route processing manager (RPM). The master RPM uses dynamic internal routing codes to facilitate the replication of multicast packets within the router. As internal routing codes are assigned, the assignments are shared with the standby RPM. Should the standby RPM have to take over as the master RPM, the new master consults the internal routing codes assigned by the previous master as the new master builds multicast state, insuring that the internal routing codes the new master assigns are consistent with those used by the prior master. This allows the multicast forwarding plane to remain available during RPM failover, without a shutdown or unstable period while the new master RPM propagates internal routing codes. Other embodiments are also described and claimed.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 1, 2013
    Assignee: Force10 Networks, Inc.
    Inventors: Srikanth Rao, Viswanathan Raman
  • Patent number: 8345439
    Abstract: A modular packet network device has a chassis in which multiple logic cards mate to the front side of an electrical signaling backplane. Logic power for the logic cards is supplied from a group of power converter cards that convert primary power to the logic voltages required by the logic cards. The power converter cards lie in a separate cooling path behind the backplane. Advantages achieved in at least some of the embodiments include removing primary power planes from the signaling backplane or portion of the backplane, providing redundant, upgradeable power modules whose individual failure does not cause logic card failure, and providing cool air to power converter circuits that would be subject to only heated air if located on the logic cards. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: January 1, 2013
    Assignee: Force10 Networks, Inc.
    Inventors: Joel R. Goergen, Donald Lewis
  • Patent number: 8346917
    Abstract: A unified enterprise level method and system for enhancing a performance of applications and storage subsystems in a storage network are disclosed. In one embodiment, a method for enhancing the performance of the storage network having applications and storage subsystems includes collecting performance data associated with the applications and the storage subsystems, and generating performance profiles for a set of combinations of the applications and the storage subsystems implemented in the storage network based on the performance data. The method also includes receiving desired performance criteria for an application of the storage network, and applying a performance profile to configure the application and a storage subsystem assigned to the application substantially similar to the desired performance criteria.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 1, 2013
    Assignee: Netapp. Inc.
    Inventors: Sridhar Balasubramanian, Ken Fugate, Richard Stehno, Mark Pokorny
  • Patent number: 8343785
    Abstract: The present disclosure provides a radiation device. The radiation device includes a first light emitting diode (LED) operable to emit light having a first central wavelength; a second LED configured adjacent the first LED and operable to emit light having a second central wavelength substantially less than the first central wavelength; and a luminescent material disposed on the first LED and the second LED. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium, lithium (Ce3+, Li+).
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Wen Yeh, Ru-Shi Liu
  • Patent number: 8345411
    Abstract: A support member includes a plate and an engaging member formed to the plate. The extends laterally and is defined by an upper surface, a lower surface and a rail that extends downward from the lower surface proximate an outer edge of the plate. The engaging member is formed to the lower surface of the plate and around a portion of the rail. The engaging member includes a surface engaging shoulder extending downward from a lower surface of the engaging member and formed around an outer surface of the engaging member. The surface engaging shoulder extends outside of and below the rail. The engaging member includes an upper shoulder formed above the surface engaging shoulder. The engaging member is configured so that the surface engaging shoulder and the upper shoulder flex upward when a force is applied downward to the upper surface of the plate.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: January 1, 2013
    Assignee: Dell Products L.P.
    Inventors: Ying-Hsien Tseng, Wen-Chi Hsu