Abstract: A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a second node. A first capacitor has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal. A second transistor has a first channel terminal coupled to the second node of the charge pump, and a second channel terminal coupled to its gate and to a third node. A second capacitor has a first terminal coupled to the second node, and a second terminal adapted to receive a second clock signal.

Abstract: An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold.

Abstract: The present invention provides a method and apparatus for providing fault-tolerance for in-circuit programming systems. The invention operates by storing a minimal set of code to initialize the in-circuit programming process in a protected memory so that if the in-circuit programming process fails, the in-circuit programming process can be restarted from the protected memory. This type of fault-tolerance is especially important in systems which allow the code which accomplishes the in-circuit programming to be modified by the in-circuit programming process. One embodiment of the present invention provides a multiplexer to selectively switch between a normal boot code sequence and a protected boot code sequence, as well as a watchdog timer to monitor the in-circuit programming process to determine whether the in-circuit programming process is not progressing properly.

Abstract: An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines arranged along the plurality of columns. The array bit lines extend across the array, and include sense lines and ground lines. A plurality of bank bit lines is arranged along the plurality of columns. The bank bit lines extend across corresponding banks in the plurality of banks and are coupled to memory cells in the corresponding banks. A plurality of connection terminals are coupled to the array bit lines. For each array bit line there is at least one connection terminal per bank in the plurality of banks for which the array bit line will be used. A plurality of bank select transistors is provided to act as bank select circuitry.

Abstract: The present invention provides an electronic file and file structure solution for comprehensive management of documents captured as scanned objects, raster objects or representation. Using the present invention a representation of a document is created using any type of imaging device. The representation includes objects present in the document. The location in the document of the objects in the plurality of objects is identified. One copy of each different object in the plurality of objects is stored in the file. The location of objects in the plurality of objects are stored in the file in a spatial layout index. The file thus contains all of the information required to faithfully reproduce the original document. In order to reconstruct the document, the objects are placed at the locations identified by the spatial layout index.

Abstract: A biopsy localization device made according to the invention includes a bioabsorbable element (34), such as a dehydrated collagen plug, delivered in a pre-delivery state to a soft tissue biopsy site (18) of a patient by an element delivery device (32). The bioabsorbable element preferably swells to fill the biopsied open region (26) and preferably is palpably harder than the surrounding soft tissue at the biopsy site. The bioabsorbable element permits the biopsy site to be relocated by palpation to eliminate the need to use metallic clips during biopsies and often eliminates the need for a return to the radiologist for pre-operative localization. In addition, the bioabsorbable element can be used as a therapeutic tool for treatment of the diseased lesion and for hemostasis.

Abstract: Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography.

Abstract: A low-stretch, flexible composite, made of one or several sections, particularly useful for making a sail (2), includes first and second polymer films (52, 62) with discontinuous, stretch-resistant segments (16) therebetween. The segments extend generally along the load lines (17) for the sail. The segments have lengths which are substantially shorter than corresponding lengths of the load lines within each section. The ends of the segments are laterally staggered relative to one another. Mats (20) of generally parallel mat elements can be used as the segments. The mat elements typically include discrete multifiber yarns (24, 26) and/or a fiber array (22), typically created by pneumatically laterally spreading apart the fibers of an untwisted multifiber yarn (32). A laminating assembly includes first and second flexible pressure sheets (66, 68), defining a sealable lamination interior (82) containing the material stack (64) to be laminated, housed within an enclosure (90).

Abstract: A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit.

Abstract: An assembly that engages a component to a computer system includes a cover adapted to retain the component and to be inserted within a chassis of the computer system. A slide movably coupled to the cover has a proximal position associated with inserting the cover into the chassis and a distal position associated with withdrawing the cover from the chassis. A detector coupled to a lock and to the slide detects movement of the slide to actuate the lock. The lock is coupled to the slide and to the detector, and blocks movement of the slide towards the distal point when the lock is in an engaged state.

Abstract: A catheter (4) includes a hollow catheter shaft (18), an inflatable balloon (36) surrounding the catheter shaft distal portion, and an expandable endoluminal prosthesis, such as a stent graft (38, 40), surrounding the balloon. The stent is typically a coiled stent having distal ends (58, 48) slidably housed within stent end holders (56, 50) on the catheter shaft. The first stent end is released from its holder by inflating the balloon. The second stent end is selectively released from its holder by other than inflating the balloon, typically by a push wire (30) pushing the second stent end out of its holder. A sheath (8) is moveable between a first position surrounding the stent and a second position spaced-apart from the stent. The stent is prevented from assuming its expanded-diameter state by (1) the engagement of the stent ends with the catheter shaft through the stent end holders, and (2) the sheath being in its first position during the introducing step.

Abstract: The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell.

Abstract: A catheter assembly includes a coiled endoluminal prosthesis (122, 190, 198) and a catheter (136) having at least first and second telescoping shafts (138, 140, 142). The prosthesis is releasably engaged to the distal ends (144, 146, 148) of the telescoping shafts. The prosthesis is capable of assuming a second, expanded diameter state from a first, reduced diameter state. The length and number of turns (128) of the coiled prosthesis can be changed by the relative translation and rotation of the shafts. The catheter assembly is especially useful for placing a coiled stent graft (122), in which one turn (132, 134) of the prosthesis has a greater pitch than the adjacent turns, at the intersection (184) of a bifurcation within a blood vessel (182). Remotely viewable marker elements (188, 190, 191, 192, 193, 195, 197) may be used and include a marker element (193, 190A, 197) configured to indicate orientation as well as axial position of the prosthesis.

Abstract: An ESD protection circuit with buried diffusion and internal overlap coupling capacitance is used to lower trigger voltage and create a compact protection circuit area. This protection circuit can be applied to memory and logic products and can be employed in power bus, input, and output pins to protect against ESD. The manufacturing process of this high-performance protection circuit is compatible with non-volatile memory process without an additional mask layer step.

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Abstract: A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cell, and a negative voltage source responsive to the supply voltage to provide a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the source voltage. The regulator maintains the negative voltage in response to the source voltage so that the electric field remains essentially constant over a range of values of source voltage.

Abstract: Medical devices that have a novel mechanical trap(s) on the distal end of a shaft that is used for the removal of material from the body. Further an expandable channel is included to entrap the material that aid with removal or obliteration of tissue or foreign bodies is disclosed.

Abstract: A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.