Abstract: A memory cell circuit has a pair of cross-coupled inverters. One inverter has an output impedance at least 10 times, preferably, at least 50 times, that of the other inverter so that during a radiation pulse the chance of a change in logic state is reduced. In a particular embodiment, the one inverter has an output impedance of 135 times that of the other inverter.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.

Abstract: A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.

Abstract: A floating gate memory device includes a substrate of semiconductor material having on a surface thereof a layer of insulating material. On the insulating layer is a floating gate of conductive polycrystalline silicon with the floating gate having a textured outer surface and relatively smoother sidewalls. A second layer of insulating material extends over the outer surface and sidewalls of the floating gate. The portion of the second insulating material over the outer surface of the floating gate has a textured surface and is thinner than the portions of the second insulating layer over the sidewalls of the floating gate. A control gate is over the second insulating layer and extends over the outer surface and sidewalls of the floating gate. The control gate is of conductive polycrystalline silicon and has an inner surface portion over the textured outer surface of the control gate which is textured and has undulations which substantially follow the undulations of the textured surface of the floating gate.

Abstract: A pulse rate monitor comprises first and second units coupled by a cable. The first unit has a microwave ocillator that provides a pulsating DC signal in accordance with the pulse rate to the second unit which amplifies the signal. Since the first unit does not comprise microwave components other than the oscillator, it can be miniturized. The second unit also supplies power to the first unit.

Abstract: An SOS integrated circuit includes a plurality of spaced islands of single-crystalline silicon on a surface of a sapphire substrate. A conformal layer of silicon oxide is on the surface of the sapphire substrate between the islands and extends along a portion of the side surfaces of the islands. A layer of polycrystalline silicon is over the silicon oxide layer and extends over the side surface and at least a portion of the top surface of the islands. A separate field-effect transistor is on each island and includes source and drain regions spaced by a channel region and a channel dielectric layer over the channel region. The polycrystalline silicon layer may extend over the channel dielectric to serve as the gate of the transistor. The method of making the circuit includes depositing the silicon oxide layer over the sapphire substrate surface and the islands, and applying a layer of a negative photoresist over the silicon oxide layer.

Abstract: The characteristics of antennas are modified by photosensitive electrical elements connected to the radiating elements. The photosensitive elements are biased by light, by direct electrical bias, or both. The photosensitive element may be a PIN diode. The bias may be applied by general illumination or conducted by a fiber optic cable.

Abstract: A digital television transmitter has a buffer that receives a low resolution low pass filtered signal. A high resolution high pass filtered signal is applied to the buffer only when the buffer can accept it without overflowing. A digital television receiver receives a digital television picture signal and preferably a transmitter buffer occupancy state signal. A low resolution low pass filtered signal is applied to an adder. A high resolution high pass filtered signal is applied to the adder when the buffer state is low and also when it is intermediate and no substantial motion is present. The transmitter and receiver are useful in video teleconferencing.

Abstract: A random access communication system forms messages to be transmitted into subpackets of fixed duration. A message packet includes two or more subpackets. Each subpacket includes information relating to the source transmitter-receiver and the number of subpackets in the message. The subpackets of the message packet are transmitted contiguously over the transmission path in a contention mode. Some subpackets are successfully received and some are lost due to collisions. After a period of asynchronous contention operation, a predetermined number of subpackets are successfully received, and the system switches to a short-term synchronous, scheduled operating mode. In the scheduled operating mode, those transmitter-receivers which were the sources of message packets including some successful and some unsuccessful subpackets retransmit the data from the unsuccessful subpackets, ordering themselves in accordance with the order of receipt of successful subpackets.

Abstract: A method of making a floating gate memory cell which relies on control gate to floating gate conduction to charge and discharge the floating gate. The gate oxide and inter-level dielectric thicknesses are independently controlled by using a mask which can compensate for the different substrate and floating gate oxidation rates.

Abstract: Indicia are formed in a sapphire substrate by ion implantation with a sufficient amount of silicon ions to establish a contrast with the remainder of the substrate. The implant is annealed at 1050.degree. to 1200.degree. C. under an oxygen or inert atmosphere. The implants are stable to repeated heatings to elevated temperature. The implants are further beneficial in that they do not introduce a source of contamination into the substrate.

Abstract: An additive that absorbs light at a given wavelength is added to a solder flux composition for use in laser soldering wherein the laser emits light of said given wavelength. The additive reduces the power required to melt the solder-flux combination and thereby improves soldering efficiency.

Abstract: Patterned glass layers which are defect-free and have smooth surfaces are formed by a method wherein a mixture of glass frit and a photoresist composition is applied to the surface of the substrate; the layer is photolithographically patterned by exposing and developing predetermined areas of the layer; then after development and prior to firing of the glass frit, the layer of material is subjected to treatment with a suitable plasma at a temperature below the thermal decomposition temperature of the photoresist composition to remove the photoresist composition from the portion of the resist layer remaining on the substrate; and then the remainder of the layer, consisting essentially of glass frit, is fired to form a smooth, defect-free, patterned glass layer over the surface of the substrate.

Abstract: A microwave planar switch matrix for selectively connecting various ones of M inputs to N outputs. The switch matrix includes a semi-insulative substrate on one side of which are conductors arranged in rows and columns, the interconnection of the rows and columns forming the intersections of the matrix, a plurality M.multidot.N of two-way active power dividers arranged in the rows near each intersection, respectively, and a plurality M.multidot.N of two-way power combiners arranged in the columns near the intersections, respectively, and M.multidot.N switches selectively connecting respectively one output of the power dividers to one input of the power combiners. Because the power dividers and power combiners utilize active components, net power gain through the matrix is possible. Air bridges separate the row and column conductors at the intersections.

Abstract: A capacitor comprises a pair of electrodes with an insulator between the electrodes. The insulator has a primary dielectric with at least one void. A fill dielectric is in the void to improve yield.A method of making a capacitor comprises forming a first electrode, forming a primary dielectric having a void over the electrode, forming a fill dielectric in the void, and forming a second electrode over the dielectrics.

Abstract: An input signal is applied to first and second logic gates to produce a first output out-of-phase with the input signal and a second output in-phase with the input signal. The first and second outputs are applied to a set/reset flip-flop whose output is applied to a transition detector to produce pulses having a minimum width when the input signal changes level for longer than some predetermined period Tl. The first and second logic gates are designed to have asymmetrical responses whereby input pulses of either polarity having less than the predetermined width Tl are treated as "noise spikes", are effectively filtered from the system, and do not cause a change in the state of the set/reset flip-flop.

Abstract: An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.

Abstract: A memory cell has a pair of cross-coupled inverters, such as a CMOS pair. Diodes are coupled in series with the transistors to reduce the possibility of radiation-induced currents in the transistors causing a change in state of the cell by providing resistance that increases the cell time constant. The transistors and the diodes are formed in the body of a semiconducting material. The diodes require at most only a small additional cell area as compared with a cell that does not have the diodes.

Abstract: A semiconductor device includes a substrate of single crystalline silicon having the active regions of a semiconductor element, such as the source, drain, channel and gates, along one surface of the substrate, and a thin gettering region of a gettering material in the substrate. The gettering region is spaced from both surfaces of the substrate and is adjacent the active regions of the semiconductor element so as to getter contaminants in the substrate from the area of the substrate containing the semiconductor element.

Abstract: In a differential pulse code modulator for image-representative signals, a coder codes difference signals to produce coded signals which have a highly variable rate, which depends upon motion in the image being represented. A rate buffer receives the coded signals and generates a control signal representative, at least in part, of the rate of fill of the rate buffer. Various filters, decimators and/or coarse quantizers associated with the modulator have characteristics controlled by the control signal in order to tend to control the rate of fill of the rate buffer. This aids in preventing loss of information at the receiver.